KMSC8122TVT6400V Freescale Semiconductor, KMSC8122TVT6400V Datasheet - Page 6

• Manufacturer Part Number: KMSC8122TVT6400V
• Description: DSP 16BIT QUAD CORE 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8122TVT6400V

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 400MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.10V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Features
6
General-Purpose I/O
I
Real-Time Operating
2
C Software Module
Global Interrupt
Controller (GIC)
Reduced Power
System (RTOS)
Semaphores
(GPIO) Port
Dissipation
Packaging
Hardware
Feature
Timers
UART
• Two signals for transmit data and receive data.
• No clock, asynchronous mode.
• Can be serviced either by the SC140 DSP cores or an external host on the system bus or the DSI.
• Full-duplex operation.
• Standard mark/space non-return-to-zero (NRZ) format.
• 13-bit baud rate selection.
• Programmable 8-bit or 9-bit data format.
• Separately enabled transmitter and receiver.
• Programmable transmitter output polarity.
• Two receiver wake-up methods:
• Separate receiver and transmitter interrupt requests.
• Eight flags, the first five can generate interrupt request:
• Receiver framing error detection.
• Hardware parity checking.
• 1/16 bit-time noise detection.
• Maximum bit rate 6.25 Mbps.
• Single-wire and loop operations.
• 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.
• Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports
• Booting from a serial EEPROM.
• Uses GPIO timing
Two modules of 16 timers each.
• Cyclic or one-shot.
• Input clock polarity control.
• Interrupt request when counting reaches a programmed threshold.
• Pulse or level interrupts.
• Dynamically updated programmed threshold.
• Read counter any time.
Watchdog mode for the timers that connect to the device.
Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism.
• Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT,
• Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.
• Generation of virtual NMI (one to each SC140 core) by a simple write access.
• Low power CMOS design.
• Separate power supply for internal logic (1.1 or 1.2 V) and I/O (3.3 V).
• Low-power standby modes.
• Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-dependent).
• 0.8 mm pitch Flip-Chip Plastic Ball-Grid Array (FC-PBGA).
• 431-connection (ball).
• Lead-free or lead-bearing spheres.
• 20 mm × 20 mm.
The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache,
timers, DMA controller, interrupts, peripherals), as follows:
• High-performance and deterministic, delivering predictive response time.
• Optimized to provide low interrupt latency with high data throughput.
• Preemptive and priority-based multitasking.
• Fully interrupt/event driven.
• Small memory footprint.
• Comprehensive set of APIs.
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open-drain output mode.
NMI_OUT, and to the cores.
Idle line wake-up.
Address mark wake-up.
Transmitter empty.
Transmission complete.
Receiver full.
Idle receiver input.
Receiver overrun.
Noise error.
Framing error.
Parity error.
MSC8122 Product Brief, Rev. 6
Description
Freescale Semiconductor