ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet - Page 6
![IC DSP CONTROLLER 32BIT 240MQFP](/photos/6/71/67190/sp-240-2_sml.jpg)
ADSP-21061KS-133
Manufacturer Part Number
ADSP-21061KS-133
Description
IC DSP CONTROLLER 32BIT 240MQFP
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21061LKSZ-160.pdf
(56 pages)
Specifications of ADSP-21061KS-133
Rohs Status
RoHS non-compliant
Interface
Synchronous Serial Port (SSP)
Clock Rate
33MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Frequency
33MHz
Supply Voltage
5V
Embedded Interface Type
HPI, Serial
No. Of Mips
50
Supply Voltage Range
4.75V To 5.25V
Operating Temperature Range
0°C To +85°C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21061KS-133
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21061/ADSP-21061L
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
CLOCK
RESET
PRIORITY
BUS
011
010
001
3
3
3
CLKIN
RESET
RPBA
ID2–0
CLKIN
RESET
RPBA
ID2–0
CLKIN
RESET
RPBA
ID2–0
ADSP-21061 #2
ADSP-21061 #1
ADSP-21061 #6
ADSP-21061 #5
ADSP-21061 #4
ADSP-21061 #3
BR1–2, BR4–6
Figure 3. Shared Memory Multiprocessing System
BR1, BR3–6
ADDR31–0
ADDR31–0
DATA47–0
DATA47–0
ADDR31–0
CONTROL
CONTROL
DATA47–0
BR2–6
MS3–0
PAGE
REDY
SBTS
CPA
BR3
WRx
ACK
BMS
HBR
HBG
BR1
CPA
RDx
BR2
CS
Rev. C | Page 6 of 56 | July 2007
5
5
5
DMA transfers between external memory and external periph-
eral devices are another option. External bus packing to 16-, 32-
, or 48-bit words is performed during DMA transfers.
ADDR
ADDR
DATA
OE
WE
ACK
CS
CS
DATA
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
BOOT EPROM (OPTIONAL)
HOST PROCESSOR
INTERFACE (OPTIONAL)