ADSP-21061KS-133 Analog Devices Inc, ADSP-21061KS-133 Datasheet - Page 39

• Manufacturer Part Number: ADSP-21061KS-133
• Description: IC DSP CONTROLLER 32BIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061KS-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Frequency: 33MHz
• Supply Voltage: 5V
• Embedded Interface Type: HPI, Serial
• No. Of Mips: 50
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 21. Serial Ports—External Clock
1
2
Table 22. Serial Ports—Internal Clock
1
2
Table 23. Serial Ports—External or Internal Clock
1
Table 24. Serial Ports—External Clock
1
Parameter
Timing Requirements
t
t
t
t
t
t
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Parameter
Timing Requirements
t
t
t
t
Referenced to sample edge.
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
t
t
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HOFSE
DFSE
HOFSE
DDTE
HODTE
TFS/RFS Setup Before TCLK/RCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
TCLK/RCLK Width
TCLK/RCLK Period
RFS Delay After RCLK (Internally Generated RFS)
RFS Hold After RCLK (Internally Generated RFS)
TFS Delay After TCLK (Internally Generated TFS)
TFS Hold After TCLK (Internally Generated TFS)
Transmit Data Delay After TCLK
Transmit Data Hold After TCLK
TFS Setup Before TCLK
TFS/RFS Hold After TCLK/RCLK
Receive Data Setup Before RCLK
Receive Data Hold After RCLK
1
; RFS Setup Before RCLK
1
1
1
1, 2
1, 2
1
1
1
Rev. C | Page 39 of 56 | July 2007
1
1
1
1
1
1
Min
3.5
4
1.5
4
9
t
Min
3
Min
3
5
Min
8
1
3
3
CK
ADSP-21061/ADSP-21061L
5 V and 3.3 V
5 V and 3.3 V
5 V and 3.3 V
5 V and 3.3 V
Max
Max
13
Max
13
16
Max
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
Unit
ns
ns
ns
ns