ADSP-21262SKBCZ200 Analog Devices Inc, ADSP-21262SKBCZ200 Datasheet - Page 38

• Manufacturer Part Number: ADSP-21262SKBCZ200
• Description: IC DSP CTLR 32BIT 136CSPBGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKBCZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• No. Of Bits: 32 Bit
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: SPI
• No. Of I/o's: 23
• Supply Voltage Range: 1.14V To 1.26V, 3.13V To 3.47V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKBCZ200

ADSP-21262
OUTPUT DRIVE CURRENTS
Figure 28
ers of the ADSP-21262. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 10 on Page 19
output disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
–10
–20
–30
–40
Figure 29. Equivalent Device Loading for AC Measurements
40
30
20
10
OUTPUT 1.5V
Figure 30. Voltage Reference Levels for AC Measurements
0
OUTPUT
0
shows typical I-V characteristics for the output driv-
INPUT
OR
Figure
PIN
V OL
TO
0.5
30. All delays (in nanoseconds) are mea-
3.47V, –45°C
SWEEP (V DDEXT ) VOLTAGE (V)
through
Figure 28. Typical Drive
1
(Includes All Fixtures)
3.11V, 125°C
1.5
Table 31 on Page
30pF
V OH
2
3.11V, 125°C
2.5
50
3.3V, 25°C
3
36. These include
3.3V, 25°C
3.47V, –45°C
Rev. B | Page 38 of 48 | August 2005
3.5
1.5V
1.5V
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
how output delays and holds vary with load capacitance (note
that this graph or derating does not apply to output disable
delays). The graphs of
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%–80%,
V=Min) vs. Load Capacitance.
12
10
0
8
6
4
2
12
10
8
6
4
2
0
0
0
Figure 32. Typical Output Rise/Fall Time
Figure 31. Typical Output Rise Time
y = 0.0467x + 1.6323
50
y = 0.049x + 1.5105
50
Figure
(20%–80%, V
(20%–80%, V
Figure
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
29).
100
31,
100
y = 0.0482x + 1.4604
y = 0.045x + 1.524
DDEXT
Figure 32
Figure
DDEXT
= Max)
= Min)
RISE
150
150
32, and
RISE
shows graphically
FALL
FALL
Figure 33
200
200
250
may
250