ADSP-21262SKBCZ200 Analog Devices Inc, ADSP-21262SKBCZ200 Datasheet - Page 36
![IC DSP CTLR 32BIT 136CSPBGA](/photos/6/71/67181/bc-136_sml.jpg)
ADSP-21262SKBCZ200
Manufacturer Part Number
ADSP-21262SKBCZ200
Description
IC DSP CTLR 32BIT 136CSPBGA
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr
Datasheet
1.ADSP-21262SKBCZ200.pdf
(48 pages)
Specifications of ADSP-21262SKBCZ200
Interface
DAI, SPI
Clock Rate
200MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
136-CSPBGA
No. Of Bits
32 Bit
Frequency
200MHz
Supply Voltage
1.2V
Embedded Interface Type
SPI
No. Of I/o's
23
Supply Voltage Range
1.14V To 1.26V, 3.13V To 3.47V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP21262SKBCZ200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21262SKBCZ200
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-21262SKBCZ200
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-21262
JTAG Test Access Port and Emulation
See
Table 31. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
CPHASE = 1
CPHASE = 0
Table 31
(OUTPUT)
(OUTPUT)
(CP = 0)
(CP = 1)
(INPUT)
(INPUT)
(INPUT)
SPICLK
(INPUT)
SPICLK
(INPUT)
SPIDS
MISO
MOSI
MISO
MOSI
and
t
S D S C O
t
Figure
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
t
t
D S O E
D S O E
D S O V
27.
t
t
S P IC H S
S S P I D S
t
t
D D S P I D S
MSB VALID
S P I C L S
MSB VALID
MSB
MSB
t
D D S P I D S
Rev. B | Page 36 of 48 | August 2005
1
t
t
S P I C H S
Figure 26. SPI Protocol—Slave
S P I C L S
2
1
t
S S P I D S
t
D D S P I D S
LSB VALID
t
t
S P I C L K S
S S P I D S
t
H D S P I D S
LSB
LSB VALID
t
H S P I D S
Min
20
5
6
7
8
4t
CK
t
H S P I D S
t
H D S
LSB
t
S D P P W
Max
7
10
t
t
t
D S D H I
H D S P I D S
D S D H I
Unit
ns
ns
ns
ns
ns
ns
ns
ns