CY39200V208-83NTXC Cypress Semiconductor Corp, CY39200V208-83NTXC Datasheet - Page 24

• Manufacturer Part Number: CY39200V208-83NTXC
• Description: IC CPLD 200K GATE 208BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V208-83NTXC

• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 136
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Voltage: 2.5V
• Memory Type: SRAM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -

Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified based on LVCMOS compliant inputs and outputs (fast slew rates).
Apply following adjustments if the inputs and outputs are configured to operate at other standards.
Document #: 38-03039 Rev. *D
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
Notes:
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
I/O Standard
0.02
t
–0.14
–0.15
–0.02
–0.22
IOD
2.75
0.16
0.14
0.41
–0.4
0.94
0.79
0.77
0.44
1.8
1.8
1.2
0.6
1.6
0
0
[16]
Fast Slew Rate
0.6
t
EA
0.05
0.7
0.1
0.3
0.2
0.4
0.2
0.9
0.8
0.5
0.6
PRELIMINARY
0
0
0
0
0
0
0
0
0
[16]
Output Delay Adjustments
t
0.9
ER
0.1
0.1
0.5
0.5
0.1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[16]
(additional delay to fast slew rate)
t
IODSLOW
2.6
2.5
2.5
2.4
2.3
2.0
1.6
2.0
2.0
2.0
2.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Slow Slew Rate
t
EASLOW
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
ERSLOW
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
IOIN
Input Delay Adjustments
0.1
0.2
0.5
0.5
0.5
0.5
0.9
0.9
0.5
0.5
0.5
0.5
0
0
0
0
0
0
0
0
0
Delta39K™ ISR™
t
CPLD Family
CKIN
0.1
0.2
0.4
0.4
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0
0
0
0
0
0
0
0
0
t
PIN
Page 24 of 91
IOREG-
0.2
0.4
0.3
0.2
0.3
0.3
0.6
0.6
0.3
0.3
0.3
0.3
0
0
0
0
0
0
0
0
0
[15]