CY39200V208-83NTXC Cypress Semiconductor Corp, CY39200V208-83NTXC Datasheet - Page 13

• Manufacturer Part Number: CY39200V208-83NTXC
• Description: IC CPLD 200K GATE 208BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39200V208-83NTXC

• Programmable Type: In-System Reprogrammable™ (ISR™) CMOS
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 3072
• Number Of Gates: 288000
• Number Of I /o: 136
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-QFP
• Voltage: 2.5V
• Memory Type: SRAM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -

Table 4. Recommended PLL Phase Shift Options
Table 5. Timing of Clock Phases for all Divide Options for a V
CompactPCI Hot Swap
The CompactPCI Hot Swap specification allows the removal
and insertion of cards into CompactPCI sockets without
switching-off the bus. Delta39K CPLDs can be used as a
CompactPCI host or target on these cards.
This feature is useful in telecommunication and networking
applications as it allows implementation of high availability
systems, where repairs and upgrades can be done without
downtime.
Delta39K CPLDs are CompactPCI Hot Swap Ready per
CompactPCI Hot Swap specification R2.0, with the following
exception:
Timing Model
One important feature of the Delta39K family is the simplicity
of its timing. All combinatorial and registered/synchronous
delays are worst case and system performance is static (as
shown in the AC specs section) as long as data is routed
through the same horizontal and vertical channels. Figure 10
illustrates the true timing model for the 200-MHz devices. For
synchronous clocking of macrocells, a delay is incurred from
macrocell clock to macrocell clock of separate Logic Blocks
within the same cluster, as well as separate Logic Blocks
within different clusters. This is respectively shown as t
t
output (from corner to corner on the device), incurs a worst-
Document #: 38-03039 Rev. *D
SCS2
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
• The I/O cells do not provide bias voltage support. External
Factor
Divide
resistors can be used to achieve this, per section 3.1.3.1 of
the CompactPCI Hot Swap specification R2.0. A simple
board level solution is provided in the application note titled
“Hot-Swapping Delta39K and Quantum38K CPLDs”.
16
1
2
3
4
5
6
8
in Figure 10. For combinatorial paths, any input to any
Period
(ns)
12
16
20
24
32
64
4
8
Duty Cycle%
40 – 60
33 – 67
40 – 60
50
50
50
50
50
Without External Feedback
PRELIMINARY
(ns)
0°
0
0
0
0
0
0
0
0
(ns)
45°
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
SCS
(ns)
and
90°
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
case delay in the 39K100 regardless of the amount of logic or
which horizontal and vertical channels are used. This is the t
shown in Figure 10. For synchronous systems, the input set-
up time to the output macrocell register and the clock to output
time are shown as the parameters t
the Figure 10. These measurements are for any output and
synchronous clock, regardless of the logic placement.
The Delta39K features:
The simple timing model of the Delta39K family eliminates
unexpected performance penalties.
Family, Package, and Density Migration in Delta39K
CPLDs
The Delta39K CPLDs combine dense logic, embedded mem-
ory and configurable I/O standards. Further design flexibility is
added by the easy migration options available between differ-
ent packages, densities and even between Quantum38K and
Delta39K CPLD families. (For details on Quantum38K CPLD
family refer to Quantum38K ISR CPLD family data sheet).
This migration flexibility makes changes or additions to de-
signs simple even after PCB layout. It also provides the ability
for experimental designs to be used on production PCBs.
Please refer to the application note titled “Family, Package,
and Density Migration in Delta39K CPLDs”.
CO
135°
• no dedicated vs. I/O pin delays
• no penalty for using 0 – 16 product terms
• no added delay for steering product terms
• no added delay for sharing product terms
• no output bypass delays
(ns)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
Output Frequency of 250 MHz
180°
(ns)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
225°
(ns)
0°
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Delta39K™ ISR™
With External Feedback
MCS
CPLD Family
270°
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
and t
MCCO
Page 13 of 91
315°
shown in
(ns)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
PD