CY39100V484B-125BBC Cypress Semiconductor Corp, CY39100V484B-125BBC Datasheet - Page 9

• Manufacturer Part Number: CY39100V484B-125BBC
• Description: IC CPLD 100K GATE 484-FBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: Delta 39K™ ISR™r

Specifications of CY39100V484B-125BBC

• Programmable Type: In-System Reprogrammable™ (ISR™) Flash
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 2.5V, 3.3V
• Number Of Macrocells: 1536
• Number Of Gates: 144000
• Number Of I /o: 302
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 484-FBGA
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: CY39100V484B-125

on the same horizontal or vertical routing channel without any
speed penalty.
In FIFO mode, the Write and Read ports are controlled by
separate clock and enable signals. The clocks for each port
are selected from four global clocks and two local clocks.
One local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs from the
Read port of the FIFO can also be registered. One clock
polarity mux per port allows using true or complement polarity
for Read and Write operations. The Write operation is
controlled by the clock and the Write enable pin. The Read
operation is controlled by the clock and the Read enable pin.
The enable pins can be sourced from horizontal or vertical
channels.
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are eight I/O
banks per device as shown in Figure 7, and all I/Os from an
I/O bank are located in the same section of a package for PCB
layout convenience.
Delta39K devices support True Vertical Migration™ (i.e., for
each package type, Delta39K devices of different densities
keep given pins in the same I/O banks). This allows for easy
and simple implementation of multiple I/O standards during
the design and prototyping phase, before a final density has
been determined. Please refer to the application note titled
“Family, Package and Density Migration in Delta 39K and
Quantum38K CPLDs”.
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
Document #: 38-03039 Rev. *D
and 512 x 8 block sizes
4K x 1, 2K x 2, 1K x 4,
Async/Sync Dual-Port
4096-bit Dual-Port
Configurable as
Configurable as
or Sync FIFO
Figure 6. Block Diagram of Channel Memory Block
PRELIMINARY
Array
inputs are driven from
the routing channels
All channel memory
Horizontal Channel
drive dedicated tracks in the
All channel memory outputs
routing channels
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To facil-
itate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a
given set of data when the device is configured at power up.
For LUT and ROM applications, the user cannot write to
memory blocks.
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure 6. This allows the channel memory blocks to be
expanded easily. These dedicated lines can be routed to I/O
pins as chip outputs or to other logic block clusters to be used
in logic equations.
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
Each I/O bank can use any supported I/O standard by
supplying appropriate V
the I/O through the Warp software. All the V
in an I/O bank must be connected to the same V
voltage respectively. This requirement restricts the number of
I/O standards supported by an I/O bank at any given time.
The number of I/Os which can be used in each I/O bank
depend on the type of I/O standards and the number of V
and GND pins being used. This restriction is derived from the
electromigration limit of the V
chip. Please refer to the note on page 17 and the application
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
I/O Cell
Figure 8 is a block diagram of the Delta39K I/O cell. The I/O
cell contains a three-state input buffer, an output buffer, and a
Global Clock
REF
GCLK[3:0]
Signals
& V
Delta39K™ ISR™
CCIO
CCIO
and GND bussing on the
CPLD Family
voltages and configuring
REF
and V
REF
Page 9 of 91
and V
CCIO
CCIO
CCIO
pins