XC9572-10PQ100I Xilinx Inc, XC9572-10PQ100I Datasheet - Page 6
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XC9572-10PQ100I
Manufacturer Part Number
XC9572-10PQ100I
Description
IC CPLD 72 MCELL I-TEMP 100-PQFP
Manufacturer
Xilinx Inc
Series
XC9500r
Specifications of XC9572-10PQ100I
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
72
Number Of Gates
1600
Number Of I /o
72
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Voltage
5V
Memory Type
FLASH
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Number Of Logic Elements/cells
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC9572-10PQ100I
Manufacturer:
XILINX
Quantity:
1 760
Company:
Part Number:
XC9572-10PQ100I
Manufacturer:
XILINX
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Part Number:
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Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC9500 In-System Programmable CPLD Family
All global control signals are available to each individual
macrocell, including clock, set/reset, and output enable sig-
nals. As shown in
originates from either of three global clocks or a product
6
I/O/GCK2
I/O/GCK3
I/O/GCK1
I/O/GSR
Figure
4, the macrocell register clock
Figure 4: Macrocell Clock and Set/Reset Capability
Product Term Set
Product Term Clock
Product Term Reset
Global Set/Reset
Global Clock 1
Global Clock 2
Global Clock 3
www.xilinx.com
term clock. Both true and complement polarities of a GCK
pin can be used within the device. A GSR input is also pro-
vided to allow user registers to be set to a user-defined
state.
DS063 (v5.5) June 25, 2007
D/T
S
R
Product Specification
Macrocell
DS063_04_110501
R