XC2C128-7TQG144I Xilinx Inc, XC2C128-7TQG144I Datasheet - Page 2

• Manufacturer Part Number: XC2C128-7TQG144I
• Description: IC CR-II CPLD 128MCELL 144TQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C128-7TQG144I

• Operating Temperature: -40°C ~ 85°C
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.0ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 3000
• Number Of I /o: 100
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Features: JTAG
• Voltage: 1.8V
• Memory Type: CMOS
• No. Of Macrocells: 128
• No. Of I/o's: 100
• Propagation Delay: 5.7ns
• Global Clock Setup Time: 2.4ns
• Frequency: 244MHz
• Supply Voltage Range: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XC2C128 CoolRunner-II CPLD
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 128
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
The CoolRunner-II 128 macrocell CPLD is I/O compatible
with various JEDEC I/O standards (see
device is also 1.5V I/O compatible with the use of
Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II CPLDs are fabricated on a 0.18 micron
process technology which is derived from leading edge
FPGA product development. CoolRunner-II CPLDs employ
RealDigital technology, a design technique that makes use
of CMOS technology in both the fabrication and design
methodology. RealDigital technology employs a cascade of
CMOS gates to implement sum of products instead of tradi-
tional sense amplifier methodology. Due to this technology,
Xilinx CoolRunner-II CPLDs achieve both high-perfor-
mance and low power operation.
Supported I/O Standards
The CoolRunner-II 128 macrocell features LVCMOS,
LVTTL, SSTL and HSTL I/O implementations. See
Table 2: I
2
Notes:
1.
Typical I
16-bit up/down, Resetable binary counter (one counter per function block).
CC
CC
(mA)
vs Frequency (LVCMOS 1.8V T
40
20
0
0.019
0
0
3.97
25
50
Table
7.95
A
Figure 1: I
50
= 25°C)
1). This
Table 1
www.xilinx.com
11.92
Frequency (MHz)
100
75
(1)
CC
Frequency (MHz)
vs Frequency
15.89
for I/O standard voltages. The LVTTL I/O standard is a gen-
eral purpose EIA/JEDEC standard for 3.3V applications that
use an LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications.
Both HSTL and SSTL make use of a V
compliance. CoolRunner-II CPLDs are also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Table 1: I/O Standards for XC2C128
(1) For information on assigning Vref pins, see
(2) LVCMOS15 requires use of Schmitt-trigger inputs.
100
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
Attribute
150
23.83
150
(2)
27.80
175
Output
V
CCIO
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
200
31.93
DS093_041905
200
V
Input
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
DS093 (v3.2) March 8, 2007
35.73
250
225
Input
V
0.75
1.25
Product Specification
(1)
N/A
N/A
N/A
N/A
N/A
1.5
REF
REF
XAPP399
39.70
250
pin for JEDEC
Termination
Voltage V
Board
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
TT
R