XC2C64A-7VQG100I Xilinx Inc, XC2C64A-7VQG100I Datasheet - Page 6

• Manufacturer Part Number: XC2C64A-7VQG100I
• Description: IC CR-II CPLD 64MCELL 100-VQFP
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7VQG100I

• Features: Programmable
• Package / Case: 100-TQFP, 100-VQFP
• Mounting Type: Surface Mount
• Voltage: 1.8V
• Operating Temperature: -40°C ~ 85°C
• Number Of I /o: 64
• Memory Type: CMOS
• Programmable Type: In System Programmable
• Number Of Macrocells: 64
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Gates: 1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP

CoolRunner-II CPLD Family
software. The AIM minimizes both propagation delay and
power as it makes attachments to the various FBs.
I/O Block
I/O blocks are primarily transceivers. However, each I/O is
either automatically compliant with standard voltage ranges
or can be programmed to become so. See
detailed information on CoolRunner-II I/Os.
In addition to voltage levels, each input can selectively
arrive through Schmitt-trigger inputs. This adds a small time
delay, but substantially reduces noise on that input pin.
Approximately 500 mV of hysteresis is added when
Schmitt-trigger inputs are selected. All LVCMOS inputs can
have hysteresis input. Hysteresis also allows easy genera-
tion of external clock circuits. The Schmitt-trigger path is
best seen in
patibility with I/O standards.
Outputs can be directly driven, 3-stated or open-drain con-
figured. A choice of slow or fast slew rate output signal is
Table 5
and shows which standards require V
termination. V
Table 5: CoolRunner-II CPLD I/O Standard Summary
6
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_1
SSTL2_1
SSTL3_1
IOSTANDARD
summarizes the single ended I/O standard support
Attribute
Figure
To Macrocell
REF
Direct Input
detail is given in specific data sheets.
4. See
To AIM
Table 5
V
3.3
3.3
2.5
1.8
1.5
1.5
2.5
3.3
CCIO
Open Drain
GTS[0:3]
Disabled
Enabled
Figure 4: CoolRunner-II CPLD I/O Block Diagram
for Schmitt-trigger com-
Hysteresis
CGND
REF
CTE
PTB
Input V
values and board
4
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
XAPP382
REF
Available on 128 Macrocell Devices and Larger
From Macrocell
www.xilinx.com
for
Board Termination Voltage
also available.
age standards associated with specific part capacities. All
inputs and disabled outputs are voltage tolerant up to 3.3V.
The CoolRunner-II family supports SSTL2-1, SSTL3-1 and
HSTL-1 high-speed I/O standards in the 128-macrocell and
larger devices.
that the inputs requiring comparison to an external refer-
ence voltage are available. These I/O standards all require
V
allows any I/O pin to act as a V
layout engineer extra freedom when laying out the pins.
However, if V
tional V
potential I/O pins or board re-work. See
details regarding V
V
The Xilinx software aids designers in remaining within the
proper pin range.
REF
REF
(V
V CCIO
pins for proper operation. The CoolRunner-II CPLD
has pin-range requirements that must be observed.
0.75
1.25
N/A
N/A
N/A
N/A
N/A
1.5
TT
REF
)
pins might be required, resulting in a loss of
REF
V REF
Table 5
Figure 4
pin placement is not done properly, addi-
REF
summarizes various supported volt-
pins and their placement.
details the I/O pin, where it is noted
Global termination
DS090 (v3.1) September 11, 2008
Pullup/Bus-Hold
Schmitt-trigger Support
REF
pin, granting the board
Not optional
Not optional
Not optional
Not optional
DS090_04_121201
Optional
Optional
Optional
Optional
Product Specification
XAPP399
for
R