EPM3512AFI256-10N Altera, EPM3512AFI256-10N Datasheet - Page 11

• Manufacturer Part Number: EPM3512AFI256-10N
• Description: IC MAX 3000A CPLD 512 256-FBGA
• Manufacturer: Altera
• Series: MAX® 3000Ar

Specifications of EPM3512AFI256-10N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 32
• Number Of Macrocells: 512
• Number Of Gates: 10000
• Number Of I /o: 208
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-FBGA
• Voltage: 3.0 V ~ 3.6 V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 32
• Family Name: MAX 3000A
• # Macrocells: 512
• Number Of Usable Gates: 10000
• Frequency (max): 125MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 32
• # I/os (max): 208
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MAX 3000A Programmable Logic Device Family Data Sheet
Figure 5. MAX 3000A PIA Routing
To LAB
PIA Signals
While the routing delays of channel–based routing schemes in masked or
FPGAs are cumulative, variable, and path–dependent, the MAX 3000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri–state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or V
.
Figure 6
shows the I/O
CC
control block for MAX 3000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
Altera Corporation
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