EPM7128SQC100-15N Altera, EPM7128SQC100-15N Datasheet - Page 31

• Manufacturer Part Number: EPM7128SQC100-15N
• Description: IC MAX 7000 CPLD 128 100-PQFP
• Manufacturer: Altera
• Series: MAX® 7000r

Specifications of EPM7128SQC100-15N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 15.0ns
• Voltage Supply - Internal: 4.75 V ~ 5.25 V
• Number Of Logic Elements/blocks: 8
• Number Of Macrocells: 128
• Number Of Gates: 2500
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Voltage: 5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 8
• Family Name: MAX 7000S
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 100MHz
• Propagation Delay Time: 15ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 84
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Cpld Type: EEPROM
• No. Of Macrocells: 128
• No. Of I/o's: 84
• Propagation Delay: 15ns
• Global Clock Setup Time: 11ns
• Frequency: 76.9MHz
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2038; EPM7128SQC100-15N

Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
f
PD1
PD2
SU
H
FSU
FH
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
ODH
CNT
CNT
ACNT
ACNT
MAX
Table 19. MAX 7000 & MAX 7000E External Timing Parameters
Symbol
Input to non-registered output
I/O input to non-registered output
Global clock setup time
Global clock hold time
Global clock setup time of fast input
Global clock hold time of fast input
Global clock to output delay
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for clear and
preset
Output data hold time after clock
Minimum global clock period
Maximum internal global clock
frequency
Minimum array clock period
Maximum internal array clock
frequency
Maximum clock frequency
Parameter
Tables 19
operating conditions.
C1 = 35 pF
C1 = 35 pF
(2)
(2)
C1 = 35 pF
C1 = 35 pF
(3)
C1 = 35 pF
(5)
(5)
(6)
through
Conditions
MAX 7000 Programmable Logic Device Family Data Sheet
(4)
26
show the MAX 7000 and MAX 7000E AC
-6 Speed Grade
151.5
151.5
Min
200
5.0
0.0
2.5
0.5
2.5
2.5
2.5
2.0
3.0
3.0
3.0
1.0
Note (1)
Max
6.0
6.0
4.0
6.5
6.6
6.6
-7 Speed Grade
125.0
125.0
166.7
Min
3.0
0.5
2.0
3.0
1.0
6.0
0.0
3.0
3.0
3.0
3.0
3.0
Max
7.5
7.5
4.5
7.5
8.0
8.0
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31