EPM7128SQC100-15N Altera, EPM7128SQC100-15N Datasheet - Page 30
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EPM7128SQC100-15N
Manufacturer Part Number
EPM7128SQC100-15N
Description
IC MAX 7000 CPLD 128 100-PQFP
Manufacturer
Altera
Series
MAX® 7000r
Datasheet
1.EPM7064STC44-10.pdf
(66 pages)
Specifications of EPM7128SQC100-15N
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.75 V ~ 5.25 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
128
Number Of Gates
2500
Number Of I /o
84
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
8
Family Name
MAX 7000S
# Macrocells
128
Number Of Usable Gates
2500
Frequency (max)
100MHz
Propagation Delay Time
15ns
Number Of Logic Blocks/elements
8
# I/os (max)
84
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
Cpld Type
EEPROM
No. Of Macrocells
128
No. Of I/o's
84
Propagation Delay
15ns
Global Clock Setup Time
11ns
Frequency
76.9MHz
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2038
EPM7128SQC100-15N
EPM7128SQC100-15N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPM7128SQC100-15N
Manufacturer:
ALTERA40
Quantity:
13 527
Part Number:
EPM7128SQC100-15N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
MAX 7000 Programmable Logic Device Family Data Sheet
Figure 13. Switching Waveforms
30
t
Inputs are driven at 3 V
for a logic high and 0 V
for a logic low. All timing
characteristics are
measured at 1.5 V.
R
& t
F
< 3 ns.
(Logic Array Output)
Parallel Expander
Shared Expander
Register Output
Input or I/O Pin
Register to PIA
Data or Enable
Clock into PIA
to Logic Array
Global Clock
Logic Array
Logic Array
Logic Array
Logic Array
Output Pin
at Register
PIA Delay
Clock into
Data from
Input Pin
Clock Pin
Register
Clock at
I/O Pin
Output
Global
Delay
Delay
to Pin
Input
Combinatorial Mode
Global Clock Mode
Array Clock Mode
t
t
R
R
t
t
IN
t
t
SU
IN
IO
t
t
ACH
CH
t
t
t
t
H
t
PIA
IN
GLOB
IO
t
RD
t
t
IC
SU
t
PIA
t
t
ACL
t
CL
SEXP
t
H
t
PIA
t
OD
t
LAC
, t
LAD
t
PEXP
t
t
F
F
t
COMB
Altera Corporation
t
CLR
, t
PRE
t
OD
t
OD
t
PIA