ATF750CL-15PU Atmel, ATF750CL-15PU Datasheet - Page 14

IC PLD HS 750 GATE 5.0V 24-PDIP

ATF750CL-15PU

Manufacturer Part Number
ATF750CL-15PU
Description
IC PLD HS 750 GATE 5.0V 24-PDIP
Manufacturer
Atmel
Series
ATF750C(L)r
Datasheet

Specifications of ATF750CL-15PU

Programmable Type
In System Programmable (min 1K program/erase cycles)
Delay Time Tpd(1) Max
15.0ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Macrocells
10
Number Of I /o
10
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Features
Programmable
Voltage
5V
Memory Type
CMOS
Package
24PDIP
Family Name
ATF750CL
Device System Gates
750
Maximum Propagation Delay Time
15 ns
Number Of User I/os
10
Typical Operating Supply Voltage
5 V
Maximum Operating Frequency
41 MHz
Number Of Product Terms Per Macro
8
Delay Time
15 ns
Number Of Programmable I/os
10
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Logic Elements/cells
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATF750CL-15PU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
29. Preload of Registered Outputs
14
ATF750C(L)
The ATF750C(L)’s registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
ter high; a V
by placing a 10.25V to 10.75V signal on pin 8 on DIPs, and lead 10 on SMDs. When the clock
term is pulsed high, the data on the I/O pins is placed into the register chosen by the select pin
.
Output Pin during Preload Cycle
Level Forced on Registered
IL
will force it low, independent of the output polarity. The PRELOAD state is entered
V
V
V
V
IH
IH
IL
IL
Select Pin
State
High
High
Low
Low
IH
Register #0 State
level on the I/O pin will force the regis-
after Cycle
High
Low
X
X
Register #1 State
after Cycle
0776L–PLD–11/08
High
Low
X
X

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