EPM9560ARI240-10 Altera, EPM9560ARI240-10 Datasheet - Page 23

• Manufacturer Part Number: EPM9560ARI240-10
• Description: IC MAX 9000 CPLD 560 240-RQFP
• Manufacturer: Altera
• Series: MAX® 9000r

Specifications of EPM9560ARI240-10

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 4.5 V ~ 5.5 V
• Number Of Logic Elements/blocks: 35
• Number Of Macrocells: 560
• Number Of Gates: 12000
• Number Of I /o: 191
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-RQFP
• Voltage: 3.3V/5V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 35
• Family Name: MAX 9000
• # Macrocells: 560
• Number Of Usable Gates: 12000
• Frequency (max): 144.9MHz
• Propagation Delay Time: 10ns
• Number Of Logic Blocks/elements: 35
• # I/os (max): 191
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: RQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2365

Altera Corporation
Programming
with External
Hardware
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during
EXTEST
BYPASS
IDCODE
UESCODE
ISP Instructions
Table 10. MAX 9000 JTAG Instructions
JTAG Instruction
f
f
normal device operation, and permits an initial data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be shifted out of TDO. Supported by the EPM9320A, EPM9400, EPM9480, and
EPM9560A devices only.
Selects the user electronic signature (UESCODE) register and allows the UESCODE to
be shifted out of TDO serially. This instruction is supported by MAX 9000A devices only.
These instructions are used when programming MAX 9000 devices via the JTAG ports
with the BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam), Jam
Byte-Code File (.jbc), or Serial Vector Format (.svf) File via an embedded processor or
test equipment.
MAX 9000 devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
For more information, see the
The MAX+PLUS II software can use text- or waveform-format test vectors
created with the MAX+PLUS II Text Editor or Waveform Editor to test a
programmed device. For added design verification, designers can
perform functional testing to compare the functional behavior of a
MAX 9000 device with the results of simulation.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also provide programming support for Altera devices.
For more information, see
MAX 9000 devices support JTAG BST circuitry as specified by IEEE Std.
1149.1-1990.
MAX 9000 family. The pin-out tables starting on
location of the JTAG control pins for each device. If the JTAG interface is
not required, the JTAG pins are available as user I/O pins.
Table 10
MAX 9000 Programmable Logic Device Family Data Sheet
describes the JTAG instructions supported by the
Programming Hardware Manufacturers.
Description
Altera Programming Hardware Data
page 38
show the
Sheet.
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