ATF1508RE-7AU100 Atmel, ATF1508RE-7AU100 Datasheet - Page 7

• Manufacturer Part Number: ATF1508RE-7AU100
• Description: IC CPLD EE 128MC 5NS 100-TQFP
• Manufacturer: Atmel
• Series: ATF1508REr

Specifications of ATF1508RE-7AU100

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Macrocells: 128
• Number Of I /o: 80
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Features: Programmable
• Voltage: 1.8V, 2.5V, 3.3V
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -

Introduction
1.3
1.3.1
1-4
Design
Considerations
JTAG Interface with
Atmel-Synario
A device residing in any location in the JTAG chain can be programmed exclusive of all
others. You can use the Atmel-ISP software to place all other devices except the one to
be programmed in the JTAG Bypass mode. When the other devices are placed in this
mode, a 1-bit flow-through register appears between the TDI and TDO pins for these
devices. During a programming operation, JTAG programming data passes through
devices in the JTAG Bypass mode but is loaded into the device that is to be pro-
grammed. This allows only the device you want to program to be loaded with JEDEC
fuse data.
Performing ISP on Atmel ISP devices requires that you reserve design resources for the
JTAG interface. You will need to reserve four I/O pins for the TMS, TDI, TDO and TCK
pins. The pin numbers for these pins depend on which Atmel ISP device you are using
and its package type. Refer to Table 1-1 for pinout information. The JTAG standard also
requires that the TMS and TDI pins be pulled up for each device in the JTAG chain. The
Atmel ISP devices have an internal pull-up feature for these pins which, when enabled,
saves the need for external pull-up resistors. Once you have reserved logic resources
for the JTAG interface, you can program, verify and erase any Atmel ISP device using
the Atmel-ISP software.
Note:
Table 1-1. Atmel ISP Device JTAG Pinout
To use ISP to program Atmel devices, you must enable the JTAG interface. An optional
but recommended practice is to also enable the TMS and TDI internal pull-ups. Enabling
the JTAG interface requires choosing specific Atmel device types before compiling your
design. This procedure is outlined below for Atmel-Synario
you need to enable Atmel fitter properties for other software platforms, please contact
Atmel PLD Applications.
To enable the JTAG interface with Atmel-Synario and multi-vendor Synario, you’ll need
to select an Atmel ISP device type first. You can change fitter property settings to enable
the TDI and TMS internal pull-ups or the pin-keeper circuits.
Note:
JTAG
TDO
TMS
TCK
Pin
TDI
Even though you must reserve certain I/O pins in your design for the JTAG
interface, you can still implement buried logic functions in the macrocells associ-
ated with these pins.
If you use an Atmel ISP device type for a design that uses the JTAG interface
pins as logic I/O pins, Atmel-Synario will generate an error.
44-pin
TQFP
32
26
1
7
44-pin
PLCC
38
13
32
7
68-pin
PLCC
Atmel ATF15xx Family: ISP Devices User Guide
12
57
19
50
84-pin
PLCC
14
71
23
62
100-pin
PQFP
75
17
64
6
™
and Atmel-WinCUPL
100-pin
TQFP
73
15
62
4
160-pin
PQFP
112
22
99
9
™
. If