AD5382BST-5 Analog Devices Inc, AD5382BST-5 Datasheet - Page 32

• Manufacturer Part Number: AD5382BST-5
• Description: IC DAC 14BIT 32CH 5V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5382BST-5

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
• Settling Time: 8µs
• Number Of Bits: 14
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 65mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5382EB - BOARD EVAL FOR AD5382
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5382
AD5382 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as
an SPI master with the Clock Polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
See the PIC16/17 Microcontroller User Manual. In this example
I/O, Port RA1 is being used to pulse SYNC and enable the serial
port of the AD5382. This microcontroller transfers only eight
bits of data during each serial transfer operation; therefore, three
consecutive read/write operations may be needed depending on
the mode.
AD5382 to 8051
The AD5382 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 37 shows how the 8051 is
connected to the AD5382. Because the AD5382 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5382
requires its data to be MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
PIC16C6X/7X
SDO/RC5
SCK/RC3
SDI/RC4
Figure 36
RA1
Figure 36. AD5382-to-PIC16C6x/7x Interface
1
shows the connection diagram.
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5382
2
C
1
Rev. B | Page 32 of 40
AD5382 to ADSP-2101/ADSP-2103
Figure 38 shows a serial interface between the AD5382 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-2103
ADSP-2101/
8XC51
Figure 38. AD5382-to-ADSP-2101/ADSP-2103 Interface
1
RxD
P1.1
SCK
TxD
RFS
TFS
1
DR
DT
Figure 37. AD5382-to-8051 Interface
DVDD
DVDD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5382
AD5382
2
2
C
C
1
1