AD5382BST-5 Analog Devices Inc, AD5382BST-5 Datasheet - Page 21

• Manufacturer Part Number: AD5382BST-5
• Description: IC DAC 14BIT 32CH 5V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5382BST-5

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012)
• Settling Time: 8µs
• Number Of Bits: 14
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 65mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• For Use With: EVAL-AD5382EB - BOARD EVAL FOR AD5382
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5382 is a complete, single-supply, 32-channel voltage
output DAC that offers 14-bit resolution. The part is available
in a 100-lead LQFP package and features both a parallel and a
serial interface. This product includes an internal, software-
selectable, 1.25 V/2.5 V, 10 ppm/°C reference, which can be
used to drive the buffered reference inputs; alternatively, an
external reference can be used to drive these inputs. Internal/
external reference selection is via the CR10 bit in the control
register; CR12 selects the reference magnitude if the internal
reference is selected. All channels have an on-chip output
amplifier with rail-to-rail output capable of driving 5 kΩ in
parallel with a 200 pF load.
The architecture of a single DAC channel consists of a 14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture guar-
antees DAC monotonicity. The 14-bit binary digital code loaded
to the DAC register determines at what node on the string the
voltage is tapped off before being fed to the output amplifier.
Each channel on these devices contains independent offset and
gain control registers that allow the user to digitally trim offset
and gain. These registers give the user the ability to calibrate out
errors in the complete signal chain, including the DAC, using
the internal m and c registers, which hold the correction factors.
All channels are double buffered, allowing synchronous
updating of all channels using the LDAC pin.
block diagram of a single channel on the AD5382. The digital
input transfer function for each DAC can be represented as
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5382).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and LSB (DB0) is a zero.
n = DAC resolution (n = 14 for AD5382).
c is the14-bit offset coefficient (default is 0x2000).
INPUT DATA
x2 = [(m + 2)/2
×1 INPUT
m REG
c REG
REG
Figure 27. Single-Channel Architecture
×2
n
× x1] + (c – 2
DAC
REG
14-BIT
VREF
DAC
n – 1
)
AVDD
Figure 27
R
R
VOUT
shows a
Rev. B | Page 21 of 40
The complete transfer function for these devices can be
represented as
where:
x2 is the data-word loaded to the resistor string DAC, and
V
externally applied to the DAC REFOUT/REFIN pin. For speci-
fied performance, an external reference voltage of 2.5 V is
recommended for the AD5380-5, and 1.25 V for the AD5380-3.
DATA DECODING
The AD5382 contains a 14-bit data bus, DB13–DB0. Depend-
ing on the value of REG1 and REG0 (see Table 11), this data is
loaded into the addressed DAC input registers (x1), offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 12 to Table 14.
Table 11. Register Selection
REG1
1
1
0
0
Table 12. DAC Data Format (REG1 = 1, REG0 = 1)
11
11
10
10
01
00
00
Table 13. Offset Data Format (REG1 = 1, REG0 = 0)
11
11
10
10
01
00
00
REF
is the internal reference voltage, or the reference voltage
VOUT = 2 × V
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
DB13 to DB0
DB13 to DB0
REG0
1
0
1
0
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
REF
Register Selected
Input Data Register (x1)
Offset Register (c)
Gain Register (m)
Special Function Registers (SFRs)
× x2/2
1111
1110
0001
0000
1111
0001
0000
1111
1110
0001
0000
1111
0001
0000
n
DAC Output (V)
2 V
2 V
2 V
2 V
2 V
2 V
0
Offset (LSB)
+8191
+8190
+1
0
–1
–8191
–8192
REF
REF
REF
REF
REF
REF
× (16383/16384)
× (16382/16384)
× (8193/16384)
× (8192/16384)
× (8191/16384)
× (1/16384)
AD5382