A3950SEUTR-T Allegro, A3950SEUTR-T Datasheet - Page 12

• Manufacturer Part Number: A3950SEUTR-T
• Manufacturer: Allegro

A3950
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify
that the information being relied upon is current.
its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
Allegro products are not authorized for use as critical components in life-support devices or sys tems without express written approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for
Copyright©2005, 2006 Allegro MicroSystems, Inc.
16X
1.65
NOM
16X
0.10 [.004]
2X0.20
MIN
0.10 [.004] M C A B
0.30
0.19
.065
0.45
NOM
.008
.012
.007
.018
C
LP Package, 16 Pin TSSOP with Exposed Thermal Pad
16
16
1
1
C
A
2
2
0.65 .026
5.10
4.90
B
3
NOM
3
NOM
.118
.201
.193
.118
14X0.20
MIN
.008
3
NOM
.118
3
NOM
A
0.65
NOM
.118
0.15
0.00
.026
6.1
NOM
4.5
4.3
1.20
MAX
SEATING
PLANE
.006
.000
.240
B
DMOS Full-Bridge Motor Driver
.177
.169
.047
6.6
6.2
C
.260
.244
A Terminal #1 mark area
B Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
C Reference land pattern layout (reference IPC7351
All dimensions reference only, not for tooling use.
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
TSOP65P640X120-17M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
GAUGE PLANE
8º
0º
0.75
0.45
0.25 .010
SEATING PLANE
0.20
0.09
1
REF
.030
.018
.039
.008
.004
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
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