ICL8001G Infineon Technologies, ICL8001G Datasheet - Page 8

• Manufacturer Part Number: ICL8001G
• Description: SP000773086_DRIVER_TR_RO
• Manufacturer: Infineon Technologies

Specifications of ICL8001G

• Packages: PG-DSO-8
• Vds: -
• Rds (on): -

The voltage v
protection. Once the voltage at this pin is higher than
the threshold V
the IC is latched off after a fixed blanking time.
To achieve the switch-on at voltage valley, the voltage
from the auxiliary winding is fed to a time delay network
(the RC network consists of D
shown in typical application circuit) before it is applied
to the zero-crossing detector through the ZC pin. The
needed time delay to the main oscillation signal ∆t
should be approximately one fourth of the oscillation
period (by transformer primary inductor and drain-
source capacitor) minus the propagation delay from
thedetected zero-crossing to the switch-on of the main
switch t
This time delay should be matched by adjusting the
time constant of the RC network which is calculated as:
3.3.2
After MOSFET is turned off, there will be some
oscillation on V
on ZC pin. To avoid that the MOSFET is turned on
mistriggerred
suppression timer is implemented. The timer is
dependent on the voltage v
lower than the threshold V
applies, while a shorter time is set when the voltage v
is higher than the threshold.
3.3.2.1
After the gate drive goes to low, it can not be changed
to high during ring suppression time.
After ring suppression time, the gate drive can be
turned on when the zero crossing is detected.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps
very fast and IC can not detect a zero crossing. In this
case, a maximum off time is implemented. After gate
drive has been remained off for the period of T
gate drive will be turned on again regardless. This
function
frequency from going lower than 20kHz, otherwise
which will cause audible noise, during start up.
3.3.3
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
Version 1.0
τ
∆t
td
=
=
T
------------ t
delay
C
osc
4
zc
can
, theoretically:
Ringing suppression time
Switch on determination
Switch Off Determination
⋅
–
-------------------------------- -
R zc1
ZC
R
delay
DS
ZCOVP
zc1
by
is also used for the output overvoltage
effectively
, which will also appear on the voltage
+
⋅
R
R zc2
during off-time of the main switch,
such
zc2
ZC
ZCRS
oscillations,
prevent
. When the voltage v
zc
, a longer preset time
, R
zc1
, R
the
zc2
a
and C
OffMax
switching
ringing
Single-Stage Flyback and PFC Controller
zc
, the
ZC
[2]
[3]
as
ZC
is
8
and the common ground. The sensed voltage across
the shunt resistor v
measurement unit, and its output voltage V
compared with the voltage at pin VR. Once the voltage
V
As a result, the main power switch is switched off. The
relationship between the V
by:
To avoid mistriggering caused by the voltage spike
across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, t
applied to the output of the comparator. In other words,
once the gate drive is turned on, the minimum on time
of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, t
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
3.4
There is a cycle by cycle current limitation realized by
the current limit comparator to provide an overcurrent
detection. The source current of the MOSFET is
sensed via a sense resistor R
source current is transformed to a sense voltage V
which is fed into the pin CS. If the voltage V
an internal voltage limit, adjusted according to the
Mains voltage, the comparator immediately turns off
the gate drive.
To prevent the Current Limitation process from
distortions caused by leading edge spikes, a Leading
Edge Blanking time (t
sensing path.
A further comparator is implemented to detect
dangerous current levels (V
one or more transformer windings are shorted or if the
secondary diode is shorted. To avoid an accidental
latch off, a spike blanking time of t
the output path of the comparator.
3.4.1
When the main bus voltage increases, the switch on
time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant
primary current limit, the maximum possible output
power is increased, which the converter may have not
been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the V
to the bus voltage. This means the V
decreased when the bus voltage increases. To keep a
constant maximum input power of the converter, the
V
1
1
exceeds the voltage V
=
3,3 V
⋅
Current Limitation
Foldback Point Correction
CS
+
0,7
CS
is applied to an internal current
LEB
Functional Description
VR
) is integrated in the current
, the output flip-flop is reset.
1
CSSW
and the v
CS
CS
voltage limit according
. By means of R
) which could occur if
CSSW
CS
ICL8001G
is integrated in
May 6, 2010
is described
CS
CS
exceeds
will be
LEB
CS
OnMax
1
, is
the
[4]
CS
is
,