LFE2-12E-6QN208I Lattice, LFE2-12E-6QN208I Datasheet - Page 45

• Manufacturer Part Number: LFE2-12E-6QN208I
• Description: FPGA LatticeECP2 Family 12000 Cells 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Lattice

Specifications of LFE2-12E-6QN208I

• Package: 208PQFP
• Family Name: LatticeECP2
• Device Logic Units: 12000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 131
• Ram Bits: 226304
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-38. LatticeECP2M Banks
LatticeECP2/M devices contain two types of sysI/O buffer pairs.
1. Top (Bank 0 and Bank 1) sysI/O Buffer Pairs (Single-Ended Outputs Only)
2. Bottom (Bank 4 and Bank 5) sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input. 

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
The sysI/O buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two
V
V REF1(7)
V REF2(7)
V CCIO6
V REF1(6)
V REF2(6)
CCIO7
GND
GND
SERDES
SERDES
Quad
Quad
Bank 0
Bank 5
BOTTOM
TOP
2-42
Bank 1
Bank 4
LatticeECP2/M Family Data Sheet
SERDES
SERDES
Quad
Quad
V CCIO2
V REF1(2)
V REF2(2)
V CCIO3
V REF1(3)
V REF2(3)
V CCIO8
GND
GND
GND
Architecture