LFE2-12E-6QN208I Lattice, LFE2-12E-6QN208I Datasheet - Page 107
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LFE2-12E-6QN208I
Manufacturer Part Number
LFE2-12E-6QN208I
Description
FPGA LatticeECP2 Family 12000 Cells 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2-12E-6QN208I
Package
208PQFP
Family Name
LatticeECP2
Device Logic Units
12000
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
131
Ram Bits
226304
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-12E-6QN208I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
For Left and Right Edges of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
For Bottom Edge of the Device
P[Edge] [n-4]
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
P[Edge] [n+4]
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 15 bits
PICs Associated with
of data for the left and right edges and up to 17 bits of data for the bottom edge. In some
packages, all the potential DDR data (DQ) pins may not be available. PIC numbering
definitions are provided in the “Signal Names” column of the Signal Descriptions table.
DQS Strobe
PIO Within PIC
4-4
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDR Strobe (DQS) and
LatticeECP2/M Family Data Sheet
Data (DQ) Pins
[Edge]DQSn
[Edge]DQSn
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
Pinout Information
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