E-STLC2500DTR STMicroelectronics, E-STLC2500DTR Datasheet - Page 4

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E-STLC2500DTR

Manufacturer Part Number
E-STLC2500DTR
Description
Bluetooth Class I/Class II 48-Pin WFBGA T/R
Manufacturer
STMicroelectronics
Datasheet

Specifications of E-STLC2500DTR

Package
48WFBGA
Power Class
Class I/Class II
Lead Free Status / Rohs Status
Compliant

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0
STLC2500D
Figure 1.
Low power consumption
Communication interfaces
Clock support
ARM7TDMI
Memory organization
Ciphering support up to 128-bit key
Single power supply with internal regulators for core voltage generation
Supports 1.65 V to 2.85 V I/O systems
Auto calibration (VCO, Filters)
Ultra low power architecture with 3 different low-power levels
Deep sleep modes, including Host-power saving feature
Dual wake-up mechanism: initiated by the Host or by the Bluetooth device
Fast UART up to 4 MHz
Flexible SPI interface up to 13 MHz
PCM interface
Up to 10 additional flexibly programmable GPIOs
External interrupts possible through the GPIOs
Fast I
System clock input (digital or sine wave) at 9.6 MHz, 10 MHz, 13 MHz, 16 MHz,
16.8 MHz, 19.2 MHz, 26 MHz, 33.6 MHz or 38.4 MHz
Low power clock input at 3.2 kHz, 32 kHz or 32.768 kHz
On chip RAM, including provision for patches
On chip ROM, preloaded with SW up to HCI
STLC2500D block diagram
2
C interface as master
TM
CPU
Overview
3/5

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