STLC2415 STMicroelectronics, STLC2415 Datasheet - Page 17

• Manufacturer Part Number: STLC2415
• Description: Bluetooth Class I 1.8V 0.721Mbps 120-Pin LFBGA
• Manufacturer: STMicroelectronics

Specifications of STLC2415

• Package: 120LFBGA
• Power Class: Class I
• Maximum Data Rate: 0.721 Mbps
• Operating Supply Voltage: 1.8 V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

including internal decimator and interpolator filters. The data can be linear PCM (13-16bit), µ-Law (8bit) or
A-Law (8bit). By default the codec interface is configured as master. The encoding on the air interface is
programmable to be CVSD, A-Law or µ-Law.
The PCM block is able to manage the PCM bus with up to 3 timeslots.
In master mode, PCM clock and data can operate at 2 MHz or at 2.048 MHz to allow interfacing of stan-
dard codecs.
The four signals of the PCM interface are:
– PCM_CLK : PCM clock
– PCM_SYNC : PCM 8kHz sync
– PCM_A : PCM data
– PCM_B : PCM data
Directions of PCM_A and PCM_B are software configurable.
Figure 6. PCM (A-law, -law) Standard Mode
Figure 7. Linear Mode
Table 11. PCM Interface Timing.
PCM Interface
PCM_SYNC
PCM_SYNC
F
PCM_CLK
PCM_CLK
Symbol
F
PCM_A
PCM_B
PCM_A
PCM_B
pcm_sync
t
pcm_clk
t
t
t
t
t
t
WCH
WSH
WCL
SSC
SDC
HCD
DCD
Frequency of PCM_CLK (master)
Frequency of PCM_SYNC
High period of PCM_CLK
Low period of PCM_CLK
High period of PCM_SYNC
Setup time, PCM_SYNC high to PCM_CLK low
Setup time, PCM_A/B input valid to PCM_CLK low
Hold time, PCM_CLK low to PCM_A/B input invalid
Delay time, PCM_CLK high to PCM_A/B output valid
0
0
1
1
2
2
3
3
B
B
4
4
Description
5
5
6
6
7
7
8
8
125 s
125 s
9
9
10
10
11
11
12
12
13
13
14
14
Min
200
200
200
100
100
100
-
15
15
2048
Typ
8
Max
150
STLC2415
D02TL558
D02TL559
Unit
kHz
kHz
B
B
ns
ns
ns
ns
ns
ns
ns
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