XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 55

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

Slave Parallel Mode Timing
X-Ref Target - Figure 12
Table 51: Timing for the Slave Parallel Configuration Mode
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Notes:
1.
2.
(Open-Drain)
Setup Times
T
T
T
Hold Times
T
T
T
Clock Timing
T
T
F
SMDCC
SMCSCC
SMCCW
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
RDWR_B
PROG_B
Symbol
The numbers in this table are based on the operating conditions set forth in
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0–D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0–D7 bus.
To pause configuration, pause CCLK instead of de-asserting CSI_B. See
Loading” for more details.
D0 - D7
(Inputs)
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
Setup time on the CSI_B pin before the rising transition at the CCLK pin
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK input pin No bitstream compression
Figure 12: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
SMCCD
Byte 1
With bitstream compression
UG332,
Table
7.
Chapter 7, section “Non-Continuous SelectMAP Data
T
T
SCCH
MCCH
1/F
CCPAR
All Speed Grades
Byte n
Min
17
7
7
1
0
0
5
5
0
0
T
T
T
MCCL
SCCL
SMCCCS
Byte n+1
Max
80
80
–
–
–
–
–
–
–
–
DS529-3_02_051607
T
SMWCC
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
55