XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 50

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

Suspend Mode Timing
X-Ref Target - Figure 9
Table 44: Suspend Mode Timing Parameters
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Entering Suspend Mode
T
T
T
T
T
Exiting Suspend Mode
T
T
T
T
T
T
AWAKE_GWE1
AWAKE_GWE512
AWAKE_GTS1
AWAKE_GTS512
SUSPENDHIGH_AWAKE
SUSPENDFILTER
SUSPEND_GTS
SUSPEND_GWE
SUSPEND_DISABLE
SUSPENDLOW_AWAKE
SUSPEND_ENABLE
These parameters based on characterization.
For information on using the Spartan-3A DSP Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
Symbol
Flip-Flops, Block RAM,
SUSPEND Input
AWAKE Output
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM lock time.
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
Entering Suspend Mode
Figure 9: Suspend Mode Timing
t
SUSPEND_GWE
t
SUSPENDHIGH_AWAKE
t
SUSPEND_GTS
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Defined by SUSPEND constraint
t
SUSPEND_DISABLE
Exiting Suspend Mode
Blocked
Write Protected
t
SUSPEND_ENABLE
t
sw_gts_cycle
SUSPENDLOW_AWAKE
sw_gwe_cycle
+160
Min
–
–
–
–
–
–
–
–
–
–
3.7 to 109
t
AWAKE_GTS
4 to 108
+300
Typ
340
10
<5
67
14
57
14
7
t
DS610-3_08_061207
AWAKE_GWE
+600
Max Units
–
–
–
–
–
–
–
–
–
–
μs
μs
ns
ns
ns
ns
ns
ns
µs
ns
µs
50