ISPLSI 5256VE-125LT128I Lattice, ISPLSI 5256VE-125LT128I Datasheet - Page 8

• Manufacturer Part Number: ISPLSI 5256VE-125LT128I
• Description: CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 125MHz EECMOS Technology 3.3V 128-Pin TQFP
• Manufacturer: Lattice

Specifications of ISPLSI 5256VE-125LT128I

• Package: 128TQFP
• Family Name: ispLSI® 5000VE
• Device System Gates: 12000
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 9.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: -40 to 85 °C

Figure 6. Boundary Scan Register Circuit for I/O Pins
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
(from previous
Shift DR
SCANIN
cell)
1
0
1
0
1
0
Clock DR
(from previous
Registers
BSCAN
D
D
D
Clock DR
SCANIN
Shift DR
Input Pin
cell)
Q
Q
Q
Update DR
0
1
Latches
BSCAN
D
D
Q
Q
D
Reset
8
PROG_MODE
EXTEST
EXTEST
Specifications ispLSI 5256VE
TOE
Q
Function
Function
Normal
Normal
SCANOUT
(to next cell)
HIGHZ
OE
SCANOUT
(to next cell)
0
1
0
1
I/O Pin