ISPLSI 5256VE-125LT128I Lattice, ISPLSI 5256VE-125LT128I Datasheet - Page 7

• Manufacturer Part Number: ISPLSI 5256VE-125LT128I
• Description: CPLD ispLSI® 5000VE Family 12K Gates 256 Macro Cells 125MHz EECMOS Technology 3.3V 128-Pin TQFP
• Manufacturer: Lattice

Specifications of ISPLSI 5256VE-125LT128I

• Package: 128TQFP
• Family Name: ispLSI® 5000VE
• Device System Gates: 12000
• Number Of Macro Cells: 256
• Maximum Propagation Delay Time: 9.5 ns
• Number Of User I/os: 96
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 125 MHz
• Number Of Product Terms Per Macro: 35
• Operating Temperature: -40 to 85 °C

The ispLSI 5000VE Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
Figure 5. ispLSI 5000VE Global Clock Structure
Global Clock Distribution
(dedicated pin)
(dedicated pin)
(dedicated pin)
(shared pin)
(shared pin)
(shared pin)
IO/CLK 2
IO/CLK 3
IO0/TOE
RESET
CLK 0
CLK 1
7
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but are
also available for logic implementation through GRP
signal routing. Figure 5 shows these different clock
distribution options.
Specifications ispLSI 5256VE
CLK0
CLK1
to/from GRP
CLK2
CLK3
to/from GRP
Global Reset
to/from GRP
TOE