MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 25

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

be asserted high. After exiting, the following sequence
is needed in order to enter a new command: Maintain
NOP input conditions for a minimum of 100us. Issue
PRECHARGE commands for all banks. Issue two or
more AUTOREFRESH commands. The values of the
MODE REGISTER and EXTENDED MODE REGISTER
will be retained upon exit Deep Power Down.
CLOCK SUSPEND
access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incrimented, as
long as the clock is suspended. (See examples in Figure
25 and Figure 26.)
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
CONCURRENT auto precharge
bank while an access command with auto precharge
enabled on a first bank is executing is not allowed by
SDRAMs, unless the SDRAM supports Concurrent
Auto precharge. Micron SDRAMs support Concurrent
Auto precharge. Four cases where Concurrent Auto
precharge occurs are defined below.
READ with Auto Precharge
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
1. Interrupted by a READ (with or without auto pre-
In order to exit Deep Power Down mode, CKE must
The clock suspend mode occurs when a column
For each positive clock edge on which CKE is sam-
Clock suspend mode is exited by registering CKE
The burst read/single write mode is entered by pro-
An access command (READ or WRITE) to a second
charge): A READ to bank m will interrupt a READ
on bank n, CAS latency later. The precharge to
bank n will begin when the READ to bank m is
registered (Figure 27).
25
Figure 25: Clock Suspend During WRITE
COMMAND
Figure 26: Clock Suspend During READ
COMMAND
INTERNAL
2. Interrupted by a WRITE (with or without auto pre-
INTERNAL
ADDRESS
ADDRESS
NOTE: For this example, burst length = 4 or greater, and DM
CLOCK
CLOCK
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
charge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to pre-
vent bus contention. The precharge to bank n will
begin when the WRITE to bank m is registered
(Figure 28).
CKE
CLK
CKE
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
IN
is LOW.
DQM is LOW.
T0
BANK,
READ
COL n
NOP
T0
T1
NOP
BANK,
WRITE
COL n
T1
D
n
IN
T2
NOP
Burst
Burst
D
OUT
n
T2
MOBILE SDRAM
T3
©2003 Micron Technology, Inc. All rights reserved.
T3
D
n + 1
256Mb: x32
OUT
T4
NOP
PRELIMINARY
NOP
n + 1
T5
T4
D
NOP
IN
n + 2
D
OUT
DON’T CARE
DON’T CARE
T6
T5
n + 2
NOP
NOP
D
IN
D
n + 3
OUT