MT48H8M32LFB5-10:G Micron Technology Inc, MT48H8M32LFB5-10:G Datasheet - Page 19

• Manufacturer Part Number: MT48H8M32LFB5-10:G
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M32LFB5-10:G

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 17/8/7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 65mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
vided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a single-
cycle delay should occur between the last read data
and the WRITE command.
shown in Figure 12 and Figure 13. The DQM signal
must be asserted (HIGH) at least two clocks prior to
the WRITE command (DQM latency is two clocks for
output buffers) to suppress data-out from the READ.
Once the WRITE command is registered, the DQs will
go High-Z (or remain High-Z), regardless of the state of
the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated
the READ command. If not, the second WRITE will be
an invalid WRITE. For example, if DQM was LOW dur-
ing T4 in Figure 13 then the WRITEs at T5 and T7
would be valid, while the WRITE at T6 would be
invalid.
WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 12 shows the case where the clock fre-
quency allows for bus contention to be avoided with-
out adding a NOP cycle, and Figure 13 shows the case
where the additional NOP is needed.
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a PRE-
CHARGE command to the same bank. The PRE-
CHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 14 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until
part of the row precharge time is hidden during the
access of the last data element(s).
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
pdf: 09005aef80d460f2, source: 09005aef80cd8d41
256Mb SDRAM x32_2.fm - Rev. D 9/04 EN
Data from any READ burst may be truncated with a
The DQM input is used to avoid I/O contention, as
The DQM signal must be de-asserted prior to the
A fixed-length READ burst may be followed by, or
In the case of a fixed-length burst being executed to
t
RP is met. Note that
19
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
COMMAND
COMMAND
ADDRESS
ADDRESS
Figure 13: READ to WRITE with Extra
NOTE:
NOTE:
DQM
DQM
CLK
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CLK
DQ
Figure 12: READ to WRITE
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.
BANK,
COL n
T0
READ
T0
BANK,
COL n
READ
T1
NOP
Clock Cycle
T1
NOP
T2
NOP
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
T2
NOP
T3
NOP
256Mb: x32
t HZ
D
OUT
PRELIMINARY
n
T3
NOP
D
T4
t HZ
OUT
NOP
t CK
n
DON’T CARE
DON’T CARE
T4
BANK,
COL b
WRITE
T5
BANK,
COL b
WRITE
D
IN
D
IN
b
t
b
t
DS
DS