K4S561633CRL75000 Samsung Semiconductor, K4S561633CRL75000 Datasheet - Page 6

• Manufacturer Part Number: K4S561633CRL75000
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S561633CRL75000

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 13b
• Access Time (max): 7/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3V
• Package Type: CSP
• Operating Temp Range: -25C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

K4S561633C-R(B)L/N/P
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.
and then rounding off to the next higher integer.
Output
(Fig. 1) DC output load circuit
870
Parameter
Parameter
VDDQ
1200
30pF
CAS latency=3
CAS latency=2
CAS latency=1
V
V
(AC operating conditions unless otherwise noted)
O H
OL
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
t
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
R D L
DAL
C D L
BDL
RP
R C
D D
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
= 2.7V ~ 3.6V, T
OL
O H
= 2mA
= -2mA
- 75
15
19
19
45
65
A
=Commercial, Extended, Industrial Temperature)
0.5 x V
0.5 x V
See Fig. 2
tr/tf = 1/1
-
2.4 / 0.4
Value
tRDL + tRP
Version
Output
DDQ
DDQ
-1H
100
19
19
19
50
70
2
1
1
1
2
1
(Fig. 2) AC output load circuit
-1L
19
24
24
60
84
0
Z0 = 50
CMOS SDRAM
Rev. 1.4 Dec. 2002
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
-
Vtt = 0.5 x VDDQ
Unit
50
ns
30pF
V
V
V
Note
2,3
1
1
1
1
1
3
2
2
4
5