STK10C48-N25I Cypress Semiconductor Corp, STK10C48-N25I Datasheet - Page 4

• Manufacturer Part Number: STK10C48-N25I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK10C48-N25I

• Word Size: 8b
• Organization: 2Kx8
• Density: 16Kb
• Interface Type: Parallel
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Supply Current: 90mA
• Lead Free Status / Rohs Status: Not Compliant

March 2006
STK10C48
SRAM WRITE CYCLES #1 & #2
Note i:
Note j:
SRAM WRITE CYCLE #1: W Controlled
SRAM WRITE CYCLE #2: E Controlled
NO.
12
13
14
15
16
17
18
19
20
21
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
DATA IN
t
WLQZ
t
t
t
t
t
t
t
t
WHQX
t
WLWH
DVWH
WHDX
AVWH
WHAX
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ V
ELWH
AVWL
AVAV
#1
W
E
W
h, i
E
SYMBOLS
t
t
t
t
t
t
t
t
WLEH
ELEH
DVEH
EHDX
AVEH
EHAX
AVAV
AVEL
#2
IH
t
AVWL
t
AVEL
18
during address transitions. NE ≥ V
18
t
Alt.
t
t
t
t
t
t
t
t
t
WC
WP
CW
DW
AW
WR
WZ
OW
DH
AS
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
t
WLQZ
20
t
AVEH
17
t
AVWH
17
PARAMETER
t
WLWH
13
IH
t
ELWH
j
.
14
j
t
AVAV
t
12
AVAV
12
HIGH IMPEDANCE
t
4
ELEH
14
t
WLEH
13
HIGH IMPEDANCE
t
DVWH
15
Document Control # ML0002 rev 0.2
t
DVEH
15
DATA VALID
DATA VALID
STK10C48-25
MIN
25
20
20
10
20
0
0
0
5
MAX
10
t
STK10C48-35
WHDX
t
MIN
WHAX
16
35
25
25
12
25
0
0
0
5
19
t
EHDX
t
EHAX
16
19
(V
t
WHQX
MAX
21
13
CC
= 5.0V
STK10C48-45
MIN
45
30
30
15
30
0
0
0
5
MAX
15
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns