SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 13

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
CAPACITANCE
Vdd = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz, Recommended Operating Temperature,
VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.1V; DM input is grouped with I/O pins because DM and the I/O pins are
matched in loading.
AC OPERATING CONDITIONS
Notes: 1–5; Recommended Operating Temperature; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Clock
Clock cycle time
CK high-level width
CK low-level width
Half clock period
Clock jitter
Data
DQ output access time from CK, /CK
Data-out high-impedance window from CK, /CK
Data-out low-impedance window from CK, /CK
DQ input setup time relative to DQS
DQ input hold time relative to DQS
DQ input setup time relative to DQS
DQ input hold time relative to DQS
DQ input pulse width (for each input)
Data hold skew factor
DQ–DQS hold, DQS to first DQ to go nonvalid, per access
Data valid output window (DVW)
Data Strobe
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK, /CK
DQS falling edge to CK rising – setup time
DQS falling edge from CK rising – hold time
DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ
DQS read preamble
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching transition
Parameter
Input Capacitance: CK, /CK (PLL Inputs)
(5pF adder for board)
Input Capacitance: BA, A,
(Registered Buffer Inputs)
(5pF adder for board)
Input/Output Capacitance: DQ, DQS, /DQS, DM
(5pF adder for board)
/S, /RAS, /CAS, /WE, CKE, ODT
CL = 5
CL = 4
CL = 3
Document Part Number 61000-03657-105 November 2007 Page 13
Symbol
tDQSCK
tWPRES
tCK (5)
tCK (4)
tCK (3)
tDQSH
tWPRE
tWPST
tDQSS
tDQSL
tRPRE
tRPST
tDIPW
tDVW
tQHS
tDSS
tDSH
tDSa
tDHa
tDSb
tDHb
tAC
tQH
tCH
tCL
tHP
tJIT
tHZ
tLZ
(AC Operating Conditions continued on next page)
MIN(tCH, tCL)
tHP -tQHS
WL - 0.25
tQH -tDQSQ
tAC MIN
0.275
Min
0.45
0.45
TBD
0.15
0.35
0.35
0.35
0.25
-0.6
-0.5
0.4
0.4
0.2
0.2
0.9
0.4
0.4
5
5
5
0
DDR2-400
Symbol
CIO
CI1
CI2
WL + 0.25
tAC MAX
tAC MAX
Max
0.55
0.55
TBD
+0.6
0.45
+0.5
0.35
1.1
0.6
0.6
8
8
8
Max
8.5
8
9
Units
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
240-PIN RDIMM
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
7, 15, 22
7, 15, 22
7, 15, 22
7, 15, 22
Notes
16, 25
16, 25
16, 25
15, 17
15, 17
15, 17
12, 13
8, 10
8, 9
19
19
20
18
36
36
11