SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 12

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
IDD SPECIFICATIONS AND CONDITIONS
Symbol—Parameter/Condition
Max DDR2 IDD Values
1. For IDD0, IDD1, IDD4W, IDD4R, IDD5, and IDD7:
2. Values shown for DDR2 SDRAM components only.
3. Values will differ depending on DRAM parts used on the
4. IDD values are calculated using worst case specifications of
IDD0—Operating one bank active-precharge current; tCK =
tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH,
/CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD1—Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W.
IDD2P—Precharge power-down current; All device banks
idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
IDD2Q—Precharge quiet standby current; All device banks
idle; tCK = tCK (IDD); CKE is HIGH, /CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
IDD2N—Precharge standby current; All device banks idle; tCK
= tCK (IDD); CKE is HIGH, /CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3P—Active power-down current; All device banks open;
tCK = tCK (IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
IDD3N—Active standby current; All device banks open; tCK =
tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is HIGH,
/CS is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
In a module with more than one rank, IDDn is calculated with
one rank in the IDDn and the other ranks in IDD2N.
For IDD2P, IDD2Q, IDD2N, IDD3P, IDD3N, and IDD6:
All ranks in IDDn.
where n=corresponding IDD condition listed in Symbol column.
module.
currently available DRAMs from different manufacturers.
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
Fast PDN Exit MR[12] = 0
DDR2-400
720
810
315
360
270
72
Units
mA
mA
mA
mA
mA
mA
Document Part Number 61000-03657-105 November 2007 Page 12
(continued)
5. For Industrial Operating Temperature range,
IDD4W—Operating burst write current; All device banks
open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK
= tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH,
/CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD4R—Operating burst read current; All device banks open,
Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE
is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD5—Burst refresh current; tCK = tCK (IDD); Refresh
command at every tRFC (IDD) interval; CKE is HIGH, /CS is HIGH
between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
IDD6—Self refresh current; CK and /CK at 0V; CKE <= 0.2V;
Other control and address bus inputs are FLOATING; Data bus
inputs are FLOATING.
IDD7—Operating bank interleave read current; All device
banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL =
tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD =
tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH between
valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions
for detail.
Symbol
IDD3P
Slow PDN Exit MR[12] = 1
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
•
•
•
when T
•
•
•
•
IDD2P and IDD3P (slow) must be derated by 4 percent
IDD4R and IDD5W must be derated by 2 percent
IDD6 and IDD7 must be derated by 7 percent
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P (fast), IDD4R,
IDD4W, and IDD5W must be derated by 2 percent
IDD2P must be derated by 20 percent;
IDD3P (slow) must be derated by 30 percent
IDD6 must be derated by 80 percent
(IDD6 will increase by this amount if TCASE < 85°C and the
2x refresh option is still enabled)
T
CASE
CASE
DDR2-400
<= 0°C:
>=85°C:
1,170
1,035
1,485
1,980
108
450
72
240-PIN RDIMM
Units
mA
mA
mA
mA
mA
mA
mA