SSTV16859DGG NXP Semiconductors, SSTV16859DGG Datasheet - Page 2

• Manufacturer Part Number: SSTV16859DGG
• Manufacturer: NXP Semiconductors

Specifications of SSTV16859DGG

• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 13
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -20mA
• Low Level Output Current: 20mA
• Package Type: TSSOP
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 200(Min)MHz
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with
differential clock inputs, designed to operate between 2.3 V and
2.7 V. All inputs are compatible with the JEDEC standard for
SSTL_2 with V
(RESET) input. All outputs are SSTL_2, Class II compatible which
can be used for standard stub-series applications or capacitive
loads. Master reset (RESET) asynchronously resets all registers to
zero.
The SSTV16859 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
QUICK REFERENCE DATA
GND = 0 V; T
NOTE:
ORDERING INFORMATION
64-Pin Plastic TSSOP
96-Ball Plastic LFBGA
56-Terminal Plastic HVQFN
2002 Feb 19
Stub-series terminated logic for 2.5 V V
Optimized for stacked DDR (Double Data Rate) SDRAM
applications
Supports SSTL_2 signal inputs as per JESD 8–9
Flow-through architecture optimizes PCB layout
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Supports efficient low power standby operation
Full DDR 200/266 solution for stacked DIMMs at 2.5 V when used
with PCKV857
See SSTV16857 for JEDEC compliant register support in
unstacked DIMM applications
See SSTV16856 for driver/buffer version with mode select.
2.5 V 13-bit to 26-bit SSTL_2
registered buffer for stacked DDR DIMM
f
i
PD
= input frequency in MHz; C
(C
SYMBOL
L
t
is used to determine the dynamic power dissipation (P
PHL
C
V
/t
CC
I
amb
PLH
REF
2
PACKAGES
= 25 C; t
f
normally at 0.5*V
o
) = sum of the outputs.
Propagation delay; CLK to Qn
Input capacitance
r
= t
f
L
2.5 ns
= output load capacity in pF; f
DD
, except the LVCMOS reset
PARAMETER
DD
(SSTL_2)
TEMPERATURE RANGE
0 to +70 C
0 to +70 C
0 to +70 C
D
in W) P
o
= output frequency in MHz; V
C
V
L
CC
2
= 30 pF; V
D
= 2.5 V
= C
The clock input is fully differential (CK and CK) to be compatible with
device even before a stable clock has been supplied, the device has
DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of
266 MHz.
The device data inputs consist of different receivers. One differential
input is tied to the input pin while the other is tied to a reference
input pad, which is shared by all inputs.
DRAM devices that are installed on the DIMM. Data are registered
at the crossing of CK going high, and CK going low. However, since
the control inputs to the SDRAM change at only half the data rate,
the device must only change state on the positive transition of the
CK signal. In order to be able to provide defined outputs from the
an asynchronous input pin (RESET), which when held to the LOW
state, resets all registers and all outputs to the LOW state.
The device supports low-power standby operation. When RESET is
low, the differential input receivers are disabled, and undriven
(floating) data, clock, and reference voltage (V
allowed. In addition, when RESET is low, all registers are reset, and
all outputs are forced low. The LVCMOS RESET input must always
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the low state during
power-up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CK and CK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
low. As long as the data inputs are low, and the clock is stable
during the time from the low-to-high transition of RESET until the
input receivers are fully enabled, the outputs will remain low.
Available in 64-pin plastic thin shrink small outline package.
CONDITIONS
PD
DD
V
CC
= 2.5 V
2
SSTV16859DGG
f
i
ORDER CODE
SSTV16859EC
SSTV16859BS
+
CC
(C
= supply voltage in V;
L
V
CC
2
TYPICAL
f
o
) where:
2.4
2.7
SSTV16859
REF
DWG NUMBER
) inputs are
SOT646AA1
853–2233 27756
SOT536-1
SOT684-1
Product data
UNIT
pF
ns