K4S161622D-TC10000 Samsung Semiconductor, K4S161622D-TC10000 Datasheet - Page 3

• Manufacturer Part Number: K4S161622D-TC10000
• Manufacturer: Samsung Semiconductor

Specifications of K4S161622D-TC10000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

K4S161622D
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
FUNCTIONAL BLOCK DIAGRAM
clock
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
-. CAS Latency ( 2 & 3)
ADD
CLK
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
K4S161622D-TC/L55
K4S161622D-TC/L60
K4S161622D-TC/L70
K4S161622D-TC/L80
K4S161622D-TC/L10
Latency & Burst Length
GENERAL DESCRIPTION
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Programming Register
WE
Data Input Register
The K4S161622D is 16,777,216 bits synchronous high data
Column Decoder
512K x 16
512K x 16
Part NO.
L(U)DQM
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
CMOS SDRAM
Rev 1.5 Sep. '00
LDQM
Interface Package
LVTTL
DQi
LWE
LDQM
TSOP(II)
50