MT47H256M8THN-3:H Micron Technology Inc, MT47H256M8THN-3:H Datasheet - Page 9

• Manufacturer Part Number: MT47H256M8THN-3:H
• Description: IC SDRAM 2GBIT 667MHZ 63FBGA
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT47H256M8THN-3:H

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 2G (256M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 63-TFBGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 7:
PDF: 09005aef83fa94e3/Source: 09005aef8266ac6e
2Gb_twindie_H.fm - Rev. B 7/10 EN
Parameter/Condition
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are floating; Data bus inputs
are floating
Operating bank interleave read current: All banks
interleaving reads; I
AL =
t
between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching (inactive die is
in I
RRD =
DD2P
t
RCD (I
t
RRD (I
condition, but with inputs switching)
DD
DDR2 I
Notes: 1–8 apply to the entire document; notes appear on page 9
DD
) - 1 ×
),
t
Notes:
RCD =
OUT
t
CK (I
CDD
= 0mA; BL = 4, CL = CL (I
t
RCD (I
DD
Specifications and Conditions (continued)
1. I
2. I
3. Data bus consists of DQ, DM, DQS, DQS#, RDQS, and RDQS#.
4. I
5. Definitions for Icdd/Idd conditions:
6. I
7. I
8. The following I
);
5b. HIGH: V
5d. Floating: Inputs at V
8b. When T
5a. LOW: V
5e. Switching: Inputs changing between HIGH and LOW every other clock cycle (once per
8a. When T
5c. Stable: Inputs stable at a HIGH or LOW level
5f. Switching: Inputs changing between HIGH and LOW every other data transfer (once per
t
V
ual die values.
operated outside of the range 0°C ≤ T
CK =
CDD
CDD
CDD
DD1
CDD
DD
DD
two clocks) for address and control signals
clock) for DQ signals, not including masks or strobes
I
and I
I
2%; I
be derated by 80% (I
option is still enabled)
); CKE is HIGH, CS# is HIGH
, I
DD2P
DD0
/I
/I
/I
/I
= V
DD
DD
DD
DD
t
DD4R
CK (I
, I
DDQ
specifications are tested after the device is properly initialized. 0°C ≤ T
parameters are specified with ODT disabled.
values must be met with all combinations of EMR bits 10 and 11.
values reflect the combined current of both individual die. I
DD6
DD2P
and I
DD1
, and I
DD
IN
C
C
IN
= +1.8V ±0.1V; V
and I
, I
≤ 0°C
≥ 85°C
≤ V
),
≥ V
must be derated by 20%; I
DD3P(SLOW)
DD2N
DD
t
RC =
IL(AC)max
DD7
IH(AC)min
DD
DD7
values must be derated (I
, I
),
require EMR1, A12 to be enabled during testing.
DD2Q
t
must be derated by 7%
RC (I
REF
DD6
must be derated by 4%; I
, I
DD
= V
DD3N
will increase by this amount if T
),
DDL
9
DDQ
Combined
, I
= +1.8V ±0.1V; V
Symbol
DD3P(FAST)
/2
I
I
CDD6
CDD7
C
Micron Technology, Inc., reserves the right to change products or specifications without notice.
≤ 85°C:
DD3P(SLOW)
DD
, I
2Gb: x4, x8 TwinDie DDR2 SDRAM
DD4R
limits increase) on IT-option devices when
I
Individual
Die Status
I
DD7
REF
DD6
, I
DD4R
I
I
must be derated by 30%; and I
CDD6
CDD7
DD4W
= V
+ I
+ I
DD2P
and I
DD6
DDQ
=
=
, and I
Electrical Specifications
/2.
DD5W
C
< 85°C and the 2X refresh
DD5W
©2010 Micron Technology, Inc. All rights reserved.
-25E
must be derated by 2%;
217
14
DDX
must be derated by
represents individ-
192
14
-3
C
≤ +85°C.
DD6
Units
mA
mA
must