STK12C68-P35I Cypress Semiconductor Corp, STK12C68-P35I Datasheet - Page 11

• Manufacturer Part Number: STK12C68-P35I
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK12C68-P35I

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 35ns
• Operating Supply Voltage (typ): 5V
• Package Type: PDIP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 75mA
• Lead Free Status / Rohs Status: Not Compliant

Document Control #ML0008 Rev 2.0
HSB OPERATION
The STK12C68, STK12C68-5 provides the HSB pin
for controlling and acknowledging the
tions. The HSB pin is used to request a hardware
STORE
STK12C68, STK12C68-5 will conditionally initiate a
STORE
will only begin if a
since the last
has a very resistive pullup and is internally driven
low to indicate a busy condition while the
(initiated by any means) is in progress.
SRAM READ
progress when HSB is driven low by any means are
given time to complete before the
is initiated. After HSB goes low, the STK12C68,
STK12C68-5 will continue
LAY
may take place. If a
is pulled low it will be allowed a time, t
plete. However, any
after HSB goes low will be inhibited until HSB
returns high.
The HSB pin can be used to synchronize multiple
STK12C68, STK12C68-5s while using a single
larger capacitor. To operate in this mode the HSB
pin should be connected together to the HSB pins
from the other STK12C68, STK12C68-5s. An exter-
nal pull-up resistor to + 5V is required since HSB
acts as an open drain pull down. The V
the other STK12C68, STK12C68-5 parts can be tied
together and share a single capacitor. The capacitor
size must be scaled by the number of devices con-
nected to it. When any one of the STK12C68,
STK12C68-5s detects a power loss and asserts
HSB, the common HSB pin will cause all parts to
request a
those STK12C68, STK12C68-5s that have been
written since the last nonvolatile cycle).
During any
was initiated, the STK12C68, STK12C68-5 will con-
tinue to drive the HSB pin low, releasing it only when
the
STORE
remain disabled until the HSB pin returns high.
. During t
STORE
June, 2008
operation after t
cycle. When the HSB pin is driven low, the
operation the STK12C68, STK12C68-5 will
STORE
STORE
DELAY
is complete. Upon completion of the
STORE
and
, multiple
cycle (a
WRITE
WRITE
WRITE
operation, regardless of how it
SRAM WRITE
or
DELAY
RECALL
STORE
is in progress when HSB
SRAM
SRAM READ
to the
; an actual
operations that are in
cycle. The HSB pin
operations for t
SRAM
STORE
cycles requested
will take place in
STORE
DELAY
STORE
CAP
took place
operations
operation
pins from
, to com-
STK12C68, STK12C68-5 (SMD5962-94599)
STORE
opera-
cycle
DE-
11
If HSB is not used, it should be left unconnected.
PREVENTING STORES
The
holding HSB high with a driver capable of sourcing
30mA at a V
overpower the internal pull-down device that drives
HSB low for 20μs at the onset of a
the STK12C68, STK12C68-5 is connected for
AutoStore operation (system V
and a 68μF capacitor on V
V
STK12C68-5 will attempt to pull HSB low; if HSB
doesn’t actually get below V
ing to pull HSB low and abort the
HARDWARE PROTECT
The STK12C68, STK12C68-5 offers hardware pro-
tection against inadvertent
SRAM WRITE
V
tions and
AutoStore can be completely disabled by tying V
to ground and applying + 5V to V
AutoStore Inhibit mode; in this mode,
only initiated by explicit request using either the soft-
ware sequence or the HSB pin.
LOW AVERAGE ACTIVE POWER
The STK12C68, STK12C68-5 draws significantly
less current when it is cycled at times longer than
50ns. Figure 4 shows the relationship between I
and
tion is shown for both
(commercial temperature range, V
duty cycle on chip enable). Figure 5 shows the
same relationship for
enable duty cycle is less than 100%, only standby
current is drawn when the chip is disabled. The
overall average current drawn by the STK12C68,
STK12C68-5 depends on the following items: 1)
CMOS
enable; 3) the overall cycle rate for accesses; 4) the
ratio of
ture; 6) the V
SWITCH
CAP
READ
STORE
< V
vs.
READ
SWITCH
on
SRAM WRITE
TTL
cycle time. Worst-case current consump-
function can be disabled on the fly by
s during low-voltage conditions. When
cc
s to
OH
, all externally initiated
the
input levels; 2) the duty cycle of chip
level; and 7) I/O loading.
of at least 2.2V, as it will have to
WRITE
way
s are inhibited.
CMOS
s; 5) the operating tempera-
WRITE
down,
IL
STORE
CAP
, the part will stop try-
and
CC
cycles. If the chip
) and V
STORE
connected to V
the
CC
TTL
CAP
operation and
STORE
STORE
= 5.5V, 100%
. This is the
STORE
STK12C68,
input levels
CC
attempt.
crosses
. When
opera-
s are
CC
CC
CC