TLE7232GNT Infineon Technologies, TLE7232GNT Datasheet - Page 26

• Manufacturer Part Number: TLE7232GNT
• Manufacturer: Infineon Technologies

Specifications of TLE7232GNT

• Switch Type: Low Side
• Power Switch Family: TLE7232G
• Input Voltage: -0.3 to 5.5V
• Power Switch On Resistance: 1Ohm
• Output Current: 240mA
• Number Of Outputs: 8
• Mounting: Surface Mount
• Supply Current: 3mA
• Package Type: DSO
• Operating Temperature (min): -40C
• Operating Temperature (max): 150C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

SPI Driver for Enhanced Relay Control
SPIDER - TLE7232G
Serial Peripheral Interface (SPI)
(SO) shifts diagnostic information out on the rising edge of the serial clock. It is essential
that the SCLK pin is in low state whenever chip select CS makes any transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit
first. SI information is read on the falling edge of SCLK. The 16 bit input data consist of
two parts (control and data). Please refer to
Section 4.4.5
for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO
is in high impedance state until the CS pin goes to low state. New data will appear at the
SO pin following the rising edge of SCLK. Please refer to
Section 4.4.5
for further
information.
4.4.2
Daisy Chain Capability
The SPI of SPIDER - TLE7232G provides daisy chain capability. In this configuration
several devices are activated by the same CS signal MCS. The SI line of one device is
connected with the SO line of another device (see
Figure
11), which builds a chain. The
ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected
to the SCLK line of each device in the chain.
device 1
device 2
device 3
SI
SO
SI
SO
SI
SO
MO
SPI
SPI
SPI
MI
MCS
MCLK
SPI_DasyChain.emf
Figure 11
Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is
shifted in each SCLK. The bit shifted out can be seen at SO. After 16 SCLK cycles, the
data transfer for one device has been finished. In single chip configuration, the CS line
must go high to make the device accept the transferred data. In daisy chain configuration
the data shifted out at device #1 has been shifted in to device #2. When using three
devices in daisy chain, three times 16 bits have to be shifted through the devices. After
that, the MCS line must go high (see
Figure
12).
Data Sheet
26
V1.2, 2009-07-15