CY7C4235-10ASC Cypress Semiconductor Corp, CY7C4235-10ASC Datasheet - Page 8

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CY7C4235-10ASC

Manufacturer Part Number
CY7C4235-10ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4235-10ASC

Lead Free Status / Rohs Status
Not Compliant
Switching Waveforms
First Data Word Latency after Reset with Simultaneous Read and Write
Empty Flag Timing
Notes:
17. When t
18. The first word is available the cycle after EF goes HIGH, always.
Q
D
0
0
Q
WCLK
D
RCLK
WEN
–D
–Q
REN
0
0
WCLK
The Latency Timing applies only at the Empty Boundary (EF = LOW).
RCLK
OE
WEN
–D
–Q
EF
REN
17
17
OE
EF
17
17
SKEW2
t
ENS
t
DS
> minimum specification, t
t
t
DS
ENS
D
0
(FIRSTVALID WRITE)
D0
t
(continued)
SKEW2
t
ENH
t
FRL
FRL
t
SKEW2
[17]
(maximum) = t
t
OLZ
t
FRL
CLK
[17]
t
+ t
REF
SKEW2
t
D
REF
. When t
1
SKEW2
8
t
t
OE
A
< minimum specification, t
t
REF
t
DS
t
ENS
t
D
A
2
FRL
(maximum) = either 2*t
D1
t
SKEW2
t
CY7C4425/4205/4215
CY7C4225/4235/4245
ENH
t
FRL
[17]
D
0
t
A
[18]
D
3
CLK
D0
+ t
SKEW2
t
REF
or t
CLK
D
42X5–9
+ t
42X5–10
1
D
SKEW2
4
.

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