CY7C4235-10ASC Cypress Semiconductor Corp, CY7C4235-10ASC Datasheet - Page 10

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CY7C4235-10ASC

Manufacturer Part Number
CY7C4235-10ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4235-10ASC

Lead Free Status / Rohs Status
Not Compliant
Switching Waveforms
Programmable Almost Empty Flag Timing
Notes:
19. PAE offset – n. Number of data words into FIFO already = n.
20. PAE offset – n.
21. t
22. If a read is performed on this rising edge of the read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
PAE
WEN2
WEN
WCLK
WCLK
rising RCLK is less than t
SKEW3
RCLK
RCLK
WEN
REN
REN
PAE
]
[19]
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
t
CLKH
SKEW3
, then PAE may not change state until the next RCLK.
(continued)
t
SKEW3
t
CLKH
t
t
ENS
ENS
[21]
t
t
ENH
ENH
t
CLKL
20
Note
t
ENS
10
t
ENH
t
PAEsynch
t
CLKL
t
PAE
t
t
ENS
ENS
n+1 WORDS
N + 1 WORDS
IN FIFO
INFIFO
t
ENS
CY7C4425/4205/4215
CY7C4225/4235/4245
t
PAE
t
ENH
n WORDS IN FIFO
Note
22
t
PAEsynch
42X5–14
42X5–13

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