DS92LV8028TUF National Semiconductor, DS92LV8028TUF Datasheet - Page 9

• Manufacturer Part Number: DS92LV8028TUF
• Manufacturer: National Semiconductor

Specifications of DS92LV8028TUF

• Number Of Elements: 8
• Number Of Receivers: 10
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 550mV
• Transmission Data Rate: 660Mbps
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
LOCK pin to the serializer’s SYNC pin. This will automati-
cally signal the serializers to send SYNC patterns whenever
the deserializer loses lock.
The user has the choice of allowing the deserializer to re-
synchronize to the data stream, or to force synchronization
by pulsing the Serializer SYNC pin. This scheme is left up to
the user discretion.
Power-down
The Power-down state is a low power sleep mode that the
Serializer and Deserializer typically occupy while waiting for
initialization, or to reduce power when there are no pending
data transfers. The DS92LV8028 serializers enter Power-
down when MS_PWDN is driven low. In Power-down, the
PLL stops and the outputs go into TRI-STATE. To exit Power-
down, the system drives MS_PWDN high.
Each of the serializers in the ’8028 also has an individual
power down, PWDNn control pin. This control enables the
deactivation of individual serializers while allowing others to
operate normally. The benefit is that spare serializers can be
allocated for backup operation, but not consuming power
until employed for data transfers.
Upon exiting Power-down, the Serializer enters the Initializa-
tion state. The system must then allow time to initialize
before data transfer can begin.
TRI-STATE
When the system drives DEN pin low, the serializer outputs
enter TRI-STATE. This will TRI-STATE the output pins
(DO0
TABLE 1. Truth Table (BIST mode)
No BIST function performed when BIST_SEL (0:3) are set from 9H to FH even when BIST_ACT is set at HIGH.
See (Note 4)
BIST_ACT
±
to DO7
H
H
H
H
H
H
H
H
H
L
L
±
). When the system drives DEN high, the
BIST_SEL
H
X
H
L
L
L
L
L
L
L
L
<
3
>
(Continued)
BIST_SEL
H
H
H
H
X
H
L
L
L
L
L
<
2
>
9
BIST_SEL
serializers will return to the previous state as long as all other
control pins remain static (PWDNn, TCLK, SYNCn, and
DINn[0:9]).
Since the high-speed LVDS serial data transmission line
quality is essential to the chipset operation, a means of
checking this signal integrity is built into the DS92LV8028
serializer. Each Serializer channel has the ability to transfer
an internally generated PRBS data pattern. This pattern
traverses the transmission line to the deserializer. Specific
deserializers (SCAN921224 for example) have the comple-
ment PRBS pattern verification circuit. The deserializer
checks the data pattern for bit errors and reports any errors
on the test verification pins on the deserializer.
The
and BIST_ACT pins together determine the functions of the
BIST mode. The BIST_ACT signal activates the test feature.
The BIST_SEL[0:2] select 1 of 8 channels as the output for
the BIST pattern. All channels perform BIST when BIS-
T_ACT = H and BIST_SEL[0:3]=08H.
The JTAG pins are reserved on this version of the serializer.
They will be JTAG compliant functionality on the next ver-
sion. The
JTAG command when available.
@
SPEED Test Feature
@
H
H
H
H
H
SPEED feature uses 5 signal pins. The BIST_SEL[0:3]
L
L
L
L
L
X
<
@
1
SPEED test will also be available through a
>
BIST_SEL
H
H
H
H
X
H
L
L
L
L
L
<
0
>
BIST on channel 0
BIST on channel 1
BIST on channel 2
BIST on channel 3
BIST on channel 4
BIST on channel 5
BIST on channel 6
BIST on channel 7
Default - NO BIST
BIST on ALL
CHANNELS
NO BIST
MODE
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