SC16C554BIBS,157 NXP Semiconductors, SC16C554BIBS,157 Datasheet - Page 27
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SC16C554BIBS,157
Manufacturer Part Number
SC16C554BIBS,157
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554BIBS157.pdf
(58 pages)
Specifications of SC16C554BIBS,157
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
NXP Semiconductors
7. Register descriptions
Table 9.
[1]
[2]
[3]
[4]
[5]
SC16C554B_554DB
Product data sheet
A2 A1 A0 Register Default
General Register set
0
0
0
0
0
0
1
1
1
1
Special Register set
0
0
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
These registers are accessible only when LCR[7] = 0.
This function is not supported in the HVQFN48 package.
Autoflow control is not supported by channel D of the HVQFN48 package, and this bit should not be written on channel D.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C554B/554DB internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
[5]
[2]
Table 9
The assigned bit functions are more fully defined in
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the SC16C554B/554DB internal registers.
[1]
Bit 7
bit 7
bit 7
0
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
All information provided in this document is subject to legal disclaimers.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
Bit 6
bit 6
bit 6
0
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
0
trans.
empty
RI
bit 6
bit 6
bit 14
Rev. 4 — 8 June 2010
0
DSR
Bit 5
bit 5
bit 5
reserved reserved
0
set
parity
autoflow
control
enable
trans.
holding
empty
bit 5
bit 5
bit 13
[4]
Bit 4
bit 4
bit 4
0
0
even
parity
loop back OP2,
break
interrupt
CTS
bit 4
bit 4
bit 12
SC16C554B/554DB
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
INTn
enable
framing
error
ΔCD
bit 3
bit 3
bit 11
Section 7.1
[3]
Bit 2
bit 2
bit 2
receive
line status
interrupt
XMIT
FIFO reset
INT
priority
bit 1
stop bits
OP1
parity error overrun
ΔRI
bit 2
bit 2
bit 10
through
© NXP B.V. 2010. All rights reserved.
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
error
ΔDSR
bit 1
bit 1
bit 9
Section
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
ΔCTS
bit 0
bit 0
bit 8
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