IS43DR16640A-25DBLI ISSI, Integrated Silicon Solution Inc, IS43DR16640A-25DBLI Datasheet - Page 15

• Manufacturer Part Number: IS43DR16640A-25DBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: DDR2 SDRAMr

Specifications of IS43DR16640A-25DBLI

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 400ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

IS43/46DR81280A, IS43/46DR16640A
AC and DC Logic Input Levels
Single‐ended DC Input Logic Level
Single‐ended AC Input logic level
Note: Refer to Overshoot and Undershoot Specification for Vpeak value: maximum peak amplitude allowed for overshoot and undershoot.
AC Input Test Conditions
Notes:
1.
2.
3.
AC Input Test Signal Waveform
Differential Input AC logic level
Notes:
1.
2.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00D, 8/17/2010
Symbol
VREF
VREF
SLEW
VID(AC)
Symbol
VIX(AC)
Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for
falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VID(AC) specifies the input differential voltage |VTR ‐VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP
is the complementary input signal (such as CK#, DQS#, LDQS# or UDQS#). The minimum value is equal to V IH(AC) ‐ V IL(AC).
The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates
the voltage at which differential input signals must cross.
VIH(DC)
Symbol
VIL(DC)
Symbol
VIH(AC)
VIL(AC)
V
AC differential crosspoint voltage
Falling Slew =
SWING(MAX)
AC differential input voltage
Input signal maximum peak to peak swing
Parameter
AC input logic HIGH
AC input logic LOW
DC input logic HIGH
DC input logic LOW
Input signal minimum slew rate
Parameter
Parameter
Input reference voltage
ΔTF
V
REF
Condition
- V
ΔTF
IL(ac)
0.5 x VDDQ‐0.175
max
VSSQ ‐ Vpeak
VREF + 0.250
Min.
0.5
DDR2‐533,667, 800
Min.
VREF + 0.125
DDR2‐533
Min.
‐ 0.3
0.5 x VDDQ+0.175
VDDQ + Vpeak
VREF ‐ 0.250
VDDQ
Max.
Rising Slew =
Max.
ΔTR
VDDQ + 0.3 V
0.5 x VDDQ
VREF ‐ 0.125
Units
V
V
Value
Max.
1.0
1.0
VSSQ ‐ Vpeak
VREF + 0.200
Notes
1, 3
V
Min.
2
IH(ac)
DDR2‐667, 800
V
V
V
V
V
V
V
min - V
ΔTR
DDQ
IH(ac)
IH(dc)
REF
IL(dc)
IL(ac)
SS
VDDQ + Vpeak
max
max
VREF ‐ 0.200
REF
min
min
Units
Max.
Units
V
V
V/ns
V
V
Notes
2, 3
Notes
Units
1
1
V
V
15