MT46H32M32LFCM-75 IT:A TR Micron Technology Inc, MT46H32M32LFCM-75 IT:A TR Datasheet - Page 76

• Manufacturer Part Number: MT46H32M32LFCM-75 IT:A TR
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H32M32LFCM-75 IT:A TR

• Organization: 32Mx32
• Density: 1Gb
• Address Bus: 13b
• Access Time (max): 6.5/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
1
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
DQSS
DQSS
DQSS
2
1. An interrupted burst of 4 is shown; 1 data element is written, 3 are masked.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
b
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
b
IN
b = data-in for column b; D
D
b
IN
T1n
NOP
T2
t
WTR
T2n
3
76
Bank a,
READ
Col b
T3
OUT
n = data-out for column n.
1Gb: x16, x32 Mobile LPDDR SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
NOP
CL = 3
CL = 3
CL = 3
Don’t Care
T5
NOP
© 2007 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
n
OUT
n
OUT
n
T6
NOP
D
n + 1
D
n + 1
D
n + 1
OUT
OUT
T6n
OUT