IS45S16320B-7CTNA1 ISSI, Integrated Silicon Solution Inc, IS45S16320B-7CTNA1 Datasheet - Page 20

• Manufacturer Part Number: IS45S16320B-7CTNA1
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS45S16320B-7CTNA1

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

at 3.3V and include a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the 134,217,728-bit banks is organized as
8,192 rows by 1024 columns by 16 bits or 8192 rows by
2048 columns by 8bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-
command are used to select the starting column location
for the burst access.
Prior to normal operation, the SDRAM must be initial-
covering device initialization, register definition, command
descriptions and device operation.
IS42S86400B, IS42/45S16320B
FUNCTIONAL DESCRIPTION
The 512Mb SDRAMs are quad-bank DRAMs which operate
A12 select the row). The address bits A0-A9 (x16); A0-A9,
A11 (x8) registered coincident with the READ or WRITE
ized. The following sections provide detailed information
20
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The 512Mb SDRAM is initialized after the power is applied
to V
with DQM High and CKE High.
A 100µs delay is required prior to issuing any command
other than a COMMAND INHIBIT or a NOP. The COMMAND
INHIBIT or NOP may be applied during the 100us period and
should continue at least through the end of the period.
With at least one COMMAND INHIBIT or NOP command
having been applied, a PRECHARGE command should
be applied once the 100µs delay has been satisfied. All
banks must be precharged. This will leave all banks in an
idle state after which at least eight AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknown state.
dd
Integrated Silicon Solution, Inc. — www.issi.com
and V
ddq
(simultaneously) and the clock is stable
10/06/2010
Rev. E