IS45S16160D-7CTNA1 ISSI, Integrated Silicon Solution Inc, IS45S16160D-7CTNA1 Datasheet - Page 30
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IS45S16160D-7CTNA1
Manufacturer Part Number
IS45S16160D-7CTNA1
Description
Manufacturer
ISSI, Integrated Silicon Solution Inc
Type
SDRAMr
Datasheet
1.IS45S16160D-7CTNA1.pdf
(64 pages)
Specifications of IS45S16160D-7CTNA1
Organization
16Mx16
Density
256Mb
Address Bus
15b
Access Time (max)
6.5/5.4ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
130mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS45S16160D-7CTNA1
Manufacturer:
ISSI
Quantity:
1 070
Part Number:
IS45S16160D-7CTNA1
Manufacturer:
ISSI
Quantity:
20 000
a longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued
until t
and address buses be available at the appropriate time to
issue the command; the advantage of the PRECHARGE
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the PRE-
CHARGE command is that it requires that the command
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated.The BURST
TERMINATE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in the READ Burst Termination diagram for each
30
rp
is met. Note that part of the row precharge time is
Integrated Silicon Solution, Inc. — www.issi.com
04/05/2010
Rev. D