MT47H128M8CF-25E:H Micron Technology Inc, MT47H128M8CF-25E:H Datasheet - Page 97
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT47H128M8CF-25E:H
Manufacturer Part Number
MT47H128M8CF-25E:H
Description
IC DDR2 SDRAM 1GBIT 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Series
-r
Datasheet
1.MT47H128M8CF-25EH.pdf
(134 pages)
Specifications of MT47H128M8CF-25E:H
Organization
128Mx8
Density
1Gb
Address Bus
17b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
125mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (128M x 8)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-TFBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H128M8CF-25E:H
Manufacturer:
SAMSUNG
Quantity:
500 000
Company:
Part Number:
MT47H128M8CF-25E:H
Manufacturer:
MICRON
Quantity:
2 890
Company:
Part Number:
MT47H128M8CF-25E:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT47H128M8CF-25E:H
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT47H128M8CF-25E:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 48: READ Interrupted by READ
Figure 49: READ-to-WRITE
READ with Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
CK#
A10
CK#
DQ
DQ
CK
CK
READ 1
Valid 4
ACT n
T0
T0
Notes:
Notes:
READ n
T1
t CCD
NOP 2
T1
CL = 3 (AL = 0)
t RCD = 3
A READ burst may be followed by a PRECHARGE command to the same bank, provided
auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-
ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and
t
prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time
from the actual READ (AL after the READ command) to PRECHARGE command. For
BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command.
Following the PRECHARGE command, a subsequent command to the same bank can-
RTP.
1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-
3. Interrupting READ command must be issued exactly 2 ×
4. READ command can be issued to any valid bank and row address (READ command at T0
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal
AL = 2
NOP
T2
sued to banks used for READs at T0 and T2.
and T2 can be either same bank or different bank).
terrupting READ command.
t
READ 3
Valid 5
Valid 4
RTP is the minimum time from the rising clock edge that initiates the last 4-bit
T2
NOP
T3
RL = 5
NOP 2
T3
CL = 3 (AL = 0)
DO
NOP
T4
CL = 3
DO
t
AC,
Valid
T4
WRITE
DO
97
t
T5
DQSCK, and
DO
Valid
T5
NOP
T6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DO
DO
n
t
DQSQ.
n + 1
DO
WL = RL - 1 = 4
DO
NOP
Valid
T7
1Gb: x4, x8, x16 DDR2 SDRAM
T6
n + 2
DO
DO
n + 3
DO
DO
NOP
T8
Valid
T7
t
CK from previous READ.
DO
Transitioning Data
Transitioning Data
© 2004 Micron Technology, Inc. All rights reserved.
NOP
T9
DI
n
DO
t
AC,
Valid
T8
n + 1
DI
DO
t
DQSCK, and
NOP
T10
n + 2
DI
DO
n + 3
Valid
DI
T9
Don’t Care
Don’t Care
NOP
T11
READ
t
DQSQ.