COM20020I3V-HT Standard Microsystems (SMSC), COM20020I3V-HT Datasheet - Page 34

• Manufacturer Part Number: COM20020I3V-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of COM20020I3V-HT

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

Revision 12-06-06
BIT
5,4
7
6
3
2
Read Bus Timing
Select
Reserved
Clock Multiplier
Enhanced
Functions
No Synchronous
BIT NAME
RBUSTMG This bit is used to Disable/Enable the High Speed CPU
CKUP1, 0
EF
NOSYNC
SYMBOL
Table 12 - Setup 2 Register
DATASHEET
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It
does not influence write operation. High speed CPU Read
operation is only for non-multiplexed bus.
This bit is undefined.
Higher frequency clocks are generated from the 20 MHz
crystal through the selection of these two bits as shown.
This clock multiplier is powered-down on default. After
changing the CKUP1 and CKUP0 bits, the ARCNET core
operation is stopped and the internal PLL in the clock
multiplier is awakened and it starts to generate the 40 MHz.
The lock out time of the internal PLL is 8μSec typically.
After 1 mS it is necessary to write command data '18H' to
command register for re-starting the ARCNET core
operation. EF bit must be ‘1’ if the data rate is over 5Mbps.
CAUTION: Changing the CKUP1 and CKUP0 bits must be
one time or less after releasing a hardware reset.
Note: After changing the CKUP1 or CKUP0 bits, it is
necessary to write a command data '18H' to the command
register. Because after changing the CKUP [1, 0] bits, the
internal operation is stopped temporarily. The writing of the
command is to start the operation.
These initializing steps are shown below.
1)
2)
3)
4)
5)
This bit is used to enable the new enhanced functions in the
COM20020I. EF = 0: Disable (Default), EF = 1: Enable. If
EF = 0, the timing and function is the same as in the
COM20020I, Revision B. See appendix “A”. EF bit must
be ‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
CKUP1
Hardware reset (Power ON)
Change CKUP[1, 0] bit
Wait 1mSec (wait until stable oscillation)
Write command '18H' (start internal operation)
Start initializing routine (Execute existing software)
0
0
1
1
34
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
CKUP0
0
1
0
1
DESCRIPTION
Clock Frequency (Data Rate)
20 MHz (Up to 2.5Mbps) Default
40 MHz (Up to 5Mbps)
Reserved
Reserved
SMSC COM20020I 3.3V